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Message-ID: <3dt5hkmi7trwyynutgkn5r3e3zips4vouhdp2fsxu6fiw44sef@kgxoyyih4tsk>
Date: Fri, 22 Aug 2025 13:17:46 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Neil Armstrong <neil.armstrong@...aro.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
        Konrad Dybcio <konradybcio@...nel.org>, Rob Herring <robh@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Conor Dooley <conor+dt@...nel.org>, linux-arm-msm@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 04/16] arm64: dts: qcom: sm8550-hdk: Set up 4-lane DP

On Fri, Aug 22, 2025 at 11:39:16AM +0200, Neil Armstrong wrote:
> Allow up to 4 lanes for the DisplayPort link from the PHYs to the
> controllers now the mode-switch events can reach the QMP Combo PHYs.
> 
> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
> ---
>  arch/arm64/boot/dts/qcom/sm8550-hdk.dts | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> index 9dfb248f9ab52b354453cf42c09d93bbee99214f..6c2c9514a7396a8b75ebe24585b47571c74ff568 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> +++ b/arch/arm64/boot/dts/qcom/sm8550-hdk.dts
> @@ -1003,7 +1003,7 @@ &mdss_dp0 {
>  };
>  
>  &mdss_dp0_out {
> -	data-lanes = <0 1>;
> +	data-lanes = <0 1 2 3>;

On most of these platforms the data lanes between DP and combo PHY are
hardwired. I'd suggest moving the data-lanes to the SoC dtsi (at least
for USB-C-wrapped DP controllers).

>  };
>  
>  &pcie0 {
> 
> -- 
> 2.34.1
> 

-- 
With best wishes
Dmitry

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