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Message-ID:
<NT0PR01MB1312E0D9EE9F158A57B77700E63D2@NT0PR01MB1312.CHNPR01.prod.partner.outlook.cn>
Date: Fri, 22 Aug 2025 06:11:33 +0000
From: Hal Feng <hal.feng@...rfivetech.com>
To: E Shattow <e@...eshell.de>, Conor Dooley <conor+dt@...nel.org>, Emil
Renner Berthing <emil.renner.berthing@...onical.com>, Heinrich Schuchardt
<heinrich.schuchardt@...onical.com>, Rob Herring <robh@...nel.org>, Krzysztof
Kozlowski <krzk+dt@...nel.org>, Palmer Dabbelt <palmer@...belt.com>, Paul
Walmsley <paul.walmsley@...ive.com>, Albert Ou <aou@...s.berkeley.edu>
CC: "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-riscv@...ts.infradead.org" <linux-riscv@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [RFC 2/3] riscv: dts: starfive: jh7110-common: Move out some
nodes to the board dts
> On 21.08.25 23:08, E Shattow wrote:
> On 8/21/25 03:09, Hal Feng wrote:
> > Some node in this file are not used by the upcoming VisionFive 2 Lite
> > board. Move them to the board dts to prepare for adding the new
> > VisionFive 2 Lite device tree.
> >
> > Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> > ---
> > .../boot/dts/starfive/jh7110-common.dtsi | 22 ---------
> > .../jh7110-deepcomputing-fml13v01.dts | 49 +++++++++++++++++++
> > .../boot/dts/starfive/jh7110-milkv-mars.dts | 49 +++++++++++++++++++
> > .../dts/starfive/jh7110-pine64-star64.dts | 49 +++++++++++++++++++
> > .../jh7110-starfive-visionfive-2.dtsi | 46 +++++++++++++++++
> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 16 ------
> > 6 files changed, 193 insertions(+), 38 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > index 2eaf01775ef5..8332622420ca 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
> > @@ -281,15 +281,9 @@ &mmc0 {
> > assigned-clock-rates = <50000000>;
> > bus-width = <8>;
> > bootph-pre-ram;
> > - cap-mmc-highspeed;
> > - mmc-ddr-1_8v;
> > - mmc-hs200-1_8v;
> > - cap-mmc-hw-reset;
> > post-power-on-delay-ms = <200>;
> > pinctrl-names = "default";
> > pinctrl-0 = <&mmc0_pins>;
> > - vmmc-supply = <&vcc_3v3>;
> > - vqmmc-supply = <&emmc_vdd>;
> > status = "okay";
> > };
> >
> > @@ -299,12 +293,7 @@ &mmc1 {
> > assigned-clock-rates = <50000000>;
> > bus-width = <4>;
> > bootph-pre-ram;
>
> > - no-sdio;
>
> drop no-sdio, it is not there in riscv-dt-for-next branch
> ref: https://lore.kernel.org/lkml/20250819-sushi-change-
> 1254c2d2a08d@...d/
OK. Thanks for pointing it out.
>
> > - no-mmc;
>
> similar, I think we should now drop no-mmc unless you can say there is a
> defect which requires it. I have tested with Star64 and Milk-V Mars CM(/-Lite);
> if you can confirm with boards you have access to that 'no-mmc' can be
> dropped then we should just drop it. The correct reason for having this 'no-
> mmc' would only be if the controller has an error when receiving these
> commands.
I tested successfully on VF2 v1.3b and VF2 Lite without "no-sdio", "no-mmc" and
"post-power-on-delay-ms". So let's drop them.
>
> > - cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > - disable-wp;
> > cap-sd-highspeed;
>
> > - post-power-on-delay-ms = <200>;
>
> I would like to know the reason for this delay configuration? Is it described
> somewhere in technical documentation or discussion why we have this?
The source of this property can not be found now. Let's drop it.
>
> > pinctrl-names = "default";
> > pinctrl-0 = <&mmc1_pins>;
> > status = "okay";
> > @@ -448,17 +437,6 @@ GPOEN_SYS_I2C6_DATA,
> > };
> >
> > mmc0_pins: mmc0-0 {
> > - rst-pins {
> > - pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > - GPOEN_ENABLE,
> > - GPI_NONE)>;
> > - bias-pull-up;
> > - drive-strength = <12>;
> > - input-disable;
> > - input-schmitt-disable;
> > - slew-rate = <0>;
> > - };
> > -
> > mmc-pins {
> > pinmux = <PINMUX(PAD_SD0_CLK, 0)>,
> > <PINMUX(PAD_SD0_CMD, 0)>,
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > index f2857d021d68..5a2a41a7e8c3 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-deepcomputing-fml13v01.dts
> > @@ -11,6 +11,55 @@ / {
> > compatible = "deepcomputing,fml13v01", "starfive,jh7110"; };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + no-sdio;
> > + no-mmc;
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > + post-power-on-delay-ms = <200>;
> > +};
> > +
> > &pcie1 {
> > perst-gpios = <&sysgpio 21 GPIO_ACTIVE_LOW>;
> > phys = <&pciephy1>;
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > index fdaf6b4557da..96f6b2f072d4 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-mars.dts
> > @@ -11,6 +11,25 @@ / {
> > compatible = "milkv,mars", "starfive,jh7110"; };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>;
> > assigned-clock-parents = <&aoncrg
> JH7110_AONCLK_GMAC0_RMII_RTX>; @@
> > -22,6 +41,36 @@ &i2c0 {
> > status = "okay";
> > };
> >
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + no-sdio;
> > + no-mmc;
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > + post-power-on-delay-ms = <200>;
> > +};
> > +
> > &pcie0 {
> > status = "okay";
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > index 31e825be2065..c9677aef9ff0 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-pine64-star64.dts
> > @@ -14,6 +14,25 @@ aliases {
> > };
> > };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > starfive,tx-use-rgmii-clk;
> > assigned-clocks = <&aoncrg JH7110_AONCLK_GMAC0_TX>; @@ -
> 44,6 +63,36
> > @@ &i2c0 {
> > status = "okay";
> > };
> >
> > +&mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > +};
> > +
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + no-sdio;
> > + no-mmc;
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > + post-power-on-delay-ms = <200>;
> > +};
> > +
> > &pcie1 {
> > status = "okay";
> > };
> > diff --git
> > a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > index 5f14afb2c24d..d1e4206f1251 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> > @@ -13,6 +13,25 @@ aliases {
> > };
> > };
> >
> > +&cpu_opp {
> > + opp-375000000 {
> > + opp-hz = /bits/ 64 <375000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-500000000 {
> > + opp-hz = /bits/ 64 <500000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-750000000 {
> > + opp-hz = /bits/ 64 <750000000>;
> > + opp-microvolt = <800000>;
> > + };
> > + opp-1500000000 {
> > + opp-hz = /bits/ 64 <1500000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > +};
> > +
> > &gmac0 {
> > status = "okay";
> > };
> > @@ -38,9 +57,36 @@ &i2c0 {
> > };
> >
> > &mmc0 {
> > + cap-mmc-highspeed;
> > + cap-mmc-hw-reset;
> > + mmc-ddr-1_8v;
> > + mmc-hs200-1_8v;
> > + vmmc-supply = <&vcc_3v3>;
> > + vqmmc-supply = <&emmc_vdd>;
> > non-removable;
> > };
> >
> > +&mmc0_pins {
> > + rst-pins {
> > + pinmux = <GPIOMUX(62, GPOUT_SYS_SDIO0_RST,
> > + GPOEN_ENABLE,
> > + GPI_NONE)>;
> > + bias-pull-up;
> > + drive-strength = <12>;
> > + input-disable;
> > + input-schmitt-disable;
> > + slew-rate = <0>;
> > + };
> > +};
> > +
> > +&mmc1 {
> > + no-sdio;
> > + no-mmc;
> > + cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
> > + disable-wp;
> > + post-power-on-delay-ms = <200>;
> > +};
> > +
> > &pcie0 {
> > status = "okay";
> > };
> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > index 0ba74ef04679..d2463399b959 100644
> > --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> > @@ -200,22 +200,6 @@ core4 {
> > cpu_opp: opp-table-0 {
> > compatible = "operating-points-v2";
> > opp-shared;
> > - opp-375000000 {
> > - opp-hz = /bits/ 64 <375000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-500000000 {
> > - opp-hz = /bits/ 64 <500000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-750000000 {
> > - opp-hz = /bits/ 64 <750000000>;
> > - opp-microvolt = <800000>;
> > - };
> > - opp-1500000000 {
> > - opp-hz = /bits/ 64 <1500000000>;
> > - opp-microvolt = <1040000>;
> > - };
> > };
> >
> > thermal-zones {
>
> With that,
>
> Reviewed-by: E Shattow <e@...eshell.de>
Thanks for your review.
Best regards,
Hal
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