[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <5950bff3-cce5-4a26-aad7-9314542f70dd@kernel.org>
Date: Fri, 22 Aug 2025 13:12:01 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Guoniu Zhou <guoniu.zhou@....com>, Rui Miguel Silva <rmfrfs@...il.com>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
Martin Kepplinger <martink@...teo.de>, Purism Kernel Team <kernel@...i.sm>,
Mauro Carvalho Chehab <mchehab@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley
<conor+dt@...nel.org>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Philipp Zabel <p.zabel@...gutronix.de>,
Frank Li <Frank.Li@....com>
Cc: linux-media@...r.kernel.org, devicetree@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 1/4] media: dt-bindings: nxp,imx8mq-mipi-csi2: Add
i.MX8ULP compatible string
On 22/08/2025 12:50, Guoniu Zhou wrote:
> The CSI-2 receiver in the i.MX8ULP is almost identical to the version
> present in the i.MX8QXP/QM. But have different reset and clock design,
> so add a device-specific compatible string for i.MX8ULP to handle the
> difference.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@....com>
> ---
> .../bindings/media/nxp,imx8mq-mipi-csi2.yaml | 42 ++++++++++++++++++++--
> 1 file changed, 40 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> index 3389bab266a9adbda313c8ad795b998641df12f3..ca485d1d596c274eb7e1f3cdc39c61bb54cc0685 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-mipi-csi2.yaml
> @@ -21,7 +21,9 @@ properties:
> - fsl,imx8mq-mipi-csi2
> - fsl,imx8qxp-mipi-csi2
> - items:
> - - const: fsl,imx8qm-mipi-csi2
> + - enum:
> + - fsl,imx8ulp-mipi-csi2
> + - fsl,imx8qm-mipi-csi2
That;s some sort of random change. Previously code was correctly sorted
- u > q... now it is not
> - const: fsl,imx8qxp-mipi-csi2
>
> reg:
> @@ -39,12 +41,19 @@ properties:
> clock that the RX DPHY receives.
> - description: ui is the pixel clock (phy_ref up to 333Mhz).
> See the reference manual for details.
> + - description: pclk is the lpav bus clock of i.MX8ULP. It provides
> + clock to CSI_REG module.
> + (see section "4.5.4 Peripheral clock diagrams,
> + Figure 76 MIPI CSI clocking" in IMX8ULPRM REV1)
> + minItems: 3
>
> clock-names:
> items:
> - const: core
> - const: esc
> - const: ui
> + - const: pclk
> + minItems: 3
>
> power-domains:
> maxItems: 1
> @@ -125,19 +134,48 @@ required:
> - ports
>
> allOf:
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8ulp-mipi-csi2
> + then:
> + properties:
> + reg:
> + minItems: 2
> + resets:
> + maxItems: 2
> + minItems: 2
minItems goes before max.
> + clocks:
> + minItems: 4
> + clock-names:
> + minItems: 4
> +
> - if:
> properties:
> compatible:
> contains:
> enum:
> - fsl,imx8qxp-mipi-csi2
> + not:
> + contains:
> + enum:
> + - fsl,imx8ulp-mipi-csi2
> then:
> properties:
> reg:
> minItems: 2
> resets:
> maxItems: 1
> - else:
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8mq-mipi-csi2
> + then:
> properties:
> reg:
> maxItems: 1
I don't see what we asked you for - restrict other variants.
Answer previous review:
"Or explain why old hardware has now 4
clocks. That explanation is missing."
>
Best regards,
Krzysztof
Powered by blists - more mailing lists