[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7mt62weitabjzhuqnqkfonztxzx4on23nbexw7xygl622r43bj@tfs47k6aohu6>
Date: Sat, 23 Aug 2025 16:21:01 +0200
From: Ondřej Jirman <megi@....cz>
To: maud_spierings@...mail.com
Cc: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
Heiko Stuebner <heiko@...ech.de>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/3] arm64: dts: rockchip: Enable the NPU on the orangepi
5 boards
Hello Maud,
On Sat, Aug 23, 2025 at 02:43:52PM +0200, Maud Spierings via B4 Relay wrote:
> From: Maud Spierings <maud_spierings@...mail.com>
>
> Enable the NPU and the PMIC that powers it.
Reviewed-by: Ondřej Jirman <megi@....cz>
> Signed-off-by: Maud Spierings <maud_spierings@...mail.com>
> ---
> .../arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi | 56 ++++++++++++++++++++++
> 1 file changed, 56 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
> index 91d56c34a1e456e18db31e1bbe7252b7e4632588..ac1df223d6a25f3059ce33970953745e402ef695 100644
> --- a/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
> +++ b/arch/arm64/boot/dts/rockchip/rk3588-orangepi-5.dtsi
> @@ -258,6 +258,28 @@ regulator-state-mem {
> };
> };
>
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c1m2_xfer>;
> + status = "okay";
> +
> + vdd_npu_s0: regulator@42 {
> + compatible = "rockchip,rk8602";
> + reg = <0x42>;
> + fcs,suspend-voltage-selector = <1>;
> + regulator-name = "vdd_npu_s0";
> + regulator-boot-on;
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <2300>;
> + vin-supply = <&vcc5v0_sys>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +};
> +
> &i2c6 {
> clock-frequency = <400000>;
> status = "okay";
> @@ -352,6 +374,40 @@ &pd_gpu {
> domain-supply = <&vdd_gpu_s0>;
> };
>
> +&pd_npu {
> + domain-supply = <&vdd_npu_s0>;
> +};
> +
> +&rknn_core_0 {
> + npu-supply = <&vdd_npu_s0>;
> + sram-supply = <&vdd_npu_s0>;
> + status = "okay";
> +};
> +
> +&rknn_core_1 {
> + npu-supply = <&vdd_npu_s0>;
> + sram-supply = <&vdd_npu_s0>;
> + status = "okay";
> +};
> +
> +&rknn_core_2 {
> + npu-supply = <&vdd_npu_s0>;
> + sram-supply = <&vdd_npu_s0>;
> + status = "okay";
> +};
> +
> +&rknn_mmu_0 {
> + status = "okay";
> +};
> +
> +&rknn_mmu_1 {
> + status = "okay";
> +};
> +
> +&rknn_mmu_2 {
> + status = "okay";
> +};
> +
> &saradc {
> vref-supply = <&vcc_1v8_s0>;
> status = "okay";
>
> --
> 2.50.1
>
>
Powered by blists - more mailing lists