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Message-Id: <202508232039.37632.pisa@fel.cvut.cz>
Date: Sat, 23 Aug 2025 20:39:37 +0200
From: Pavel Pisa <pisa@....cvut.cz>
To: Greg KH <gregkh@...uxfoundation.org>
Cc: Xu Yilun <yilun.xu@...ux.intel.com>,
jgg@...dia.com,
m.szyprowski@...sung.com,
yilun.xu@...el.com,
linux-fpga@...r.kernel.org,
mdf@...nel.org,
linux-kernel@...r.kernel.org,
Michal Simek <michal.simek@....com>,
"Marc Kleine-Budde" <mkl@...gutronix.de>,
Sebastian Andrzej Siewior <bigeasy@...utronix.de>
Subject: Re: [PATCH 1/1] fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()
Hello Greg,
On Tuesday 19 of August 2025 07:25:57 Greg KH wrote:
> On Tue, Aug 19, 2025 at 12:39:02AM +0200, Pavel Pisa wrote:
> > I have analyzed the cause and reported (August 4) that mainline
> > Zynq runtime FPGA bitstream loading was broken by patch
> >
> > 37e00703228a ("zynq_fpga: use sgtable-based scatterlist wrappers")
> >
....
> It's in my "to apply" queue to get to for 6.17-final.
>
> Please give us a chance to catch up, August is usually a time for
> vacations :)
Thanks lot for the pushing the patch
fpga: zynq_fpga: Fix the wrong usage of dma_map_sgtable()
into the Linux kernel mainline. I report success - the mainline
is not stuck after FPGA reconfiguration and CTU CAN FD tests
progress to successful finish for mainline kernel.
The exact tested version
6.17.0-rc2-g8d245acc1e88+flood-kern-fd-thrd-load
In the fact, I have noticed that your pull request has been applied
by Linus at 8/23/25 5:27 PM and I have invoked the CAN latester
build queue by had to provide feedback as soon as possible.
It is triggered after CEST midnight normally with results
available next day at the morning.
As for the stable queues (from your e-mail notices), please,
ensure that both patches are applied or none.
As for our whole test round results together with the RT kernel, we do not
reach functional state yet because the problematic patch has propagated
to RT kernel and kernel fails hard way after boot and reconfigure
script invocation now.
When FPGA configuration is skipped and then run manually on RT,
I get
[ 233.319355] dtbocfg: loading out-of-tree module taints kernel.
[ 233.319999] dtbocfg: 0.1.0
[ 233.320105] dtbocfg: OK
[ 233.435010] fpga_manager fpga0: writing system.bit.bin to Xilinx Zynq FPGA Manager
[ 233.510549] fpga_manager fpga0: Unable to DMA map (TO_DEVICE)
[ 233.510567] fpga_manager fpga0: Error while writing image data to FPGA
[ 233.510951] fpga_region region0: failed to load FPGA image
[ 233.510967] OF: overlay: overlay changeset pre-apply notifier error -12, target: /fpga-full
We build the branch "for-kbuild-bot/current-stable" from
git://git.kernel.org/pub/scm/linux/kernel/git/rt/linux-rt-devel.git
The actual version
6.17.0-rc1-rt1-gf54787e29f62
We can switch to another branch or reintroduce some patching
in the automatic process which we have there in the past.
By the way, I have done the first OpenOCD accesses/registers
dumps of our CTU CAN FD IP core on ESP32-C5 to see how it has
propagated to real silocon. We are buying some CAN FD
transceivers in DIL package for initial wire nest
soldering on a bread board now.
Best wishes,
Pavel
Pavel Pisa
phone: +420 603531357
e-mail: pisa@....felk.cvut.cz
Department of Control Engineering FEE CVUT
Karlovo namesti 13, 121 35, Prague 2
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