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Message-Id: <20250824124317.390795-1-b10902118@ntu.edu.tw>
Date: Sun, 24 Aug 2025 20:43:14 +0800
From: b10902118 <b10902118@....edu.tw>
To: oleg@...hat.com,
linux@...linux.org.uk,
catalin.marinas@....com,
will@...nel.org
Cc: linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org,
b10902118 <b10902118@....edu.tw>
Subject: [PATCH 0/3] ARM/arm64: ptrace: fix unaligned hardware breakpoint validation for 32bit
PTRACE_SETREGSET and PTRACE_SETHBPREGS fail when setting a hardware
breakpoint on a non-4-byte aligned address with a valid length to
a 32-bit tracee. The length should be valid as long as the range
started from the address is within one aligned 4 bytes.
The Cause:
The kernel modifies a breakpoint's addr and ctrl separately, but
each modification comes with validation, so the first validation
sees the user-provided addr and old ctrl (and vice versa for
PTRACE_SETHBPREGS). This combination can be invalid if the address
is unaligned and the control's length is too long (ex: the 4-byte
default).
The kernel only checks the alignment for 32-bit tracees, so this only
happens to them.
The Fix:
1. Fix PTRACE_SETREGSET by modifying addr and ctrl together.
2. Mitigate PTRACE_SETHBPREGS by minimizing default length.
This cannot be fixed without removing or relaxing the alignment
check because partially modified breakpoints are unavoidable for
PTRACE_SETHBPREGS, which receives either addr or ctrl per call.
b10902118 (3):
arm64: ptrace: fix hw_break_set() by setting addr and ctrl together
arm64: ptrace: minimize default bp_len for hw breakpoints to pass
check
ARM: ptrace: minimize default bp_len for hw breakpoints to pass check
arch/arm/kernel/ptrace.c | 16 ++++++++++++-
arch/arm64/kernel/ptrace.c | 49 ++++++++++++++++++++++++++++++++------
2 files changed, 57 insertions(+), 8 deletions(-)
--
2.50.1
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