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Message-Id: <20250825-msm-dp-mst-v3-12-01faacfcdedd@oss.qualcomm.com>
Date: Mon, 25 Aug 2025 22:15:58 +0800
From: Yongxing Mou <yongxing.mou@....qualcomm.com>
To: Rob Clark <robin.clark@....qualcomm.com>,
Dmitry Baryshkov <lumag@...nel.org>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Sean Paul <sean@...rly.run>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
Yongxing Mou <yongxing.mou@....qualcomm.com>,
Abhinav Kumar <quic_abhinavk@...cinc.com>
Subject: [PATCH v3 12/38] drm/msm/dp: introduce max_streams for DP
controller MST support
From: Abhinav Kumar <quic_abhinavk@...cinc.com>
Introduce the `mst_streams` field in each DP controller descriptor to
specify the number of supported MST streams. Most platforms support 2 or
4 MST streams, while platforms without MST support default to a single
stream (`DEFAULT_STREAM_COUNT = 1`).
This change also accounts for platforms with asymmetric stream support,
e.g., DP0 supporting 4 streams and DP1 supporting 2.
Signed-off-by: Abhinav Kumar <quic_abhinavk@...cinc.com>
Signed-off-by: Yongxing Mou <yongxing.mou@....qualcomm.com>
---
drivers/gpu/drm/msm/dp/dp_display.c | 21 +++++++++++++++++++++
drivers/gpu/drm/msm/dp/dp_display.h | 1 +
2 files changed, 22 insertions(+)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c
index 78d932bceb581ee54116926506b1025bd159108f..a8477a0a180137f15cbb1401c3964636aa32626c 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.c
+++ b/drivers/gpu/drm/msm/dp/dp_display.c
@@ -33,6 +33,7 @@ module_param(psr_enabled, bool, 0);
MODULE_PARM_DESC(psr_enabled, "enable PSR for eDP and DP displays");
#define HPD_STRING_SIZE 30
+#define DEFAULT_STREAM_COUNT 1
enum {
ISR_DISCONNECTED,
@@ -52,6 +53,7 @@ struct msm_dp_display_private {
bool core_initialized;
bool phy_initialized;
bool audio_supported;
+ bool mst_supported;
struct drm_device *drm_dev;
@@ -84,12 +86,15 @@ struct msm_dp_display_private {
void __iomem *p0_base;
size_t p0_len;
+
+ int max_stream;
};
struct msm_dp_desc {
phys_addr_t io_start;
unsigned int id;
bool wide_bus_supported;
+ int mst_streams;
};
static const struct msm_dp_desc msm_dp_desc_sa8775p[] = {
@@ -1213,6 +1218,15 @@ static int msm_dp_display_get_io(struct msm_dp_display_private *display)
return 0;
}
+int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display)
+{
+ struct msm_dp_display_private *dp;
+
+ dp = container_of(msm_dp_display, struct msm_dp_display_private, msm_dp_display);
+
+ return dp->max_stream;
+}
+
static int msm_dp_display_probe(struct platform_device *pdev)
{
int rc = 0;
@@ -1239,6 +1253,13 @@ static int msm_dp_display_probe(struct platform_device *pdev)
dp->msm_dp_display.is_edp =
(dp->msm_dp_display.connector_type == DRM_MODE_CONNECTOR_eDP);
dp->hpd_isr_status = 0;
+ dp->max_stream = DEFAULT_STREAM_COUNT;
+ dp->mst_supported = FALSE;
+
+ if (desc->mst_streams > DEFAULT_STREAM_COUNT) {
+ dp->max_stream = desc->mst_streams;
+ dp->mst_supported = TRUE;
+ }
rc = msm_dp_display_get_io(dp);
if (rc)
diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h
index 37c6e87db90ce951274cdae61f26d76dc9ef3840..7727cf325a89b4892d2370a5616c4fa76fc88485 100644
--- a/drivers/gpu/drm/msm/dp/dp_display.h
+++ b/drivers/gpu/drm/msm/dp/dp_display.h
@@ -29,6 +29,7 @@ struct msm_dp {
bool psr_supported;
};
+int msm_dp_get_mst_max_stream(struct msm_dp *msm_dp_display);
int msm_dp_display_get_modes(struct msm_dp *msm_dp_display);
bool msm_dp_display_check_video_test(struct msm_dp *msm_dp_display);
int msm_dp_display_get_test_bpp(struct msm_dp *msm_dp_display);
--
2.34.1
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