linux-kernel - Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd extension descriptions

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Message-ID: <b812bb46-6a26-456a-8210-d02138fb31a6@isrc.iscas.ac.cn>
Date: Tue, 26 Aug 2025 00:19:40 +0800
From: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
To: inochiama@...il.com
Cc: ajones@...tanamicro.com, alex@...ti.fr, anup@...infault.org,
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Subject: Re: [PATCH v1 RESEND 1/5] dt-bidings: riscv: add Zilsd and Zclsd
 extension descriptions

On 2025/8/23 6:34, Inochi Amaoto wrote:
 > On Thu, Aug 21, 2025 at 10:01:27PM +0800, Pincheng Wang wrote:
 >> Add descriptions for the Zilsd (Load/Store pair instructions) and
 >> Zclsd (Compressed Load/Store pair instructions) ISA extensions
 >> which were ratified in commit f88abf1 ("Integrating load/store
 >> pair for RV32 with the main manual") of the riscv-isa-manual.
 >>
 >> Signed-off-by: Pincheng Wang <pincheng.plct@...c.iscas.ac.cn>
 >> ---
 >>   .../devicetree/bindings/riscv/extensions.yaml | 39 +++++++++++++++++++
 >>   1 file changed, 39 insertions(+)
 >>
 >> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml 
b/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> index ede6a58ccf53..d72ffe8f6fa7 100644
 >> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
 >> @@ -366,6 +366,20 @@ properties:
 >>               guarantee on LR/SC sequences, as ratified in commit 
b1d806605f87
 >>               ("Updated to ratified state.") of the riscv profiles 
specification.
 >>
 >> +        - const: zilsd
 >> +          description:
 >> +            The standard Zilsd extension which provides support for 
aligned
 >> +            register-pair load and store operations in 32-bit 
instruction
 >> +            encodings, as ratified in commit f88abf1 ("Integrating
 >> +            load/store pair for RV32 with the main manual") of 
riscv-isa-manual.
 >> +
 >> +        - const: zclsd
 >> +          description:
 >> +            The Zclsd extension implements the compressed (16-bit) 
version of the
 >> +            Load/Store Pair for RV32. As with Zilsd, this extension 
was ratified
 >> +            in commit f88abf1 ("Integrating load/store pair for 
RV32 with the
 >> +            main manual") of riscv-isa-manual.
 >> +
 >>           - const: zk
 >>             description:
 >>               The standard Zk Standard Scalar cryptography extension 
as ratified
 >> @@ -847,6 +861,16 @@ properties:
 >>               anyOf:
 >>                 - const: v
 >>                 - const: zve32x
 >
 >> +      # Zclsd depends on Zilsd and Zca
 >> +      - if:
 >> +          contains:
 >> +            anyOf:
 >> +              - const: zclsd
 >> +        then:
 >> +          contains:
 >> +            anyOf:
 >> +              - const: zilsd
 >> +              - const: zca
 >>
 >
 > Should be allOf? I see the comment says "Zclsd" requires both "Zilsd"
 > and "Zca".
 >
 > Regards,
 > Inochi

You're absolutely right, thank you for catching this. Since Zclsd 
depends on both Zilsd and Zca, the condition should use allOf to 
correctly enforce the conjunction. I'll fix this in next revision.

Best regards,
Pincheng Wang