linux-kernel - Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4

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Message-ID: <9139A302-ADF6-4E2C-917E-0E0E1D6CBA0A@gmail.com>
Date: Mon, 25 Aug 2025 07:26:55 +0300
From: Svyatoslav <clamor95@...il.com>
To: Mikko Perttunen <mperttunen@...dia.com>
CC: Thierry Reding <thierry.reding@...il.com>,
 Jonathan Hunter <jonathanh@...dia.com>,
 Peter De Schrijver <pdeschrijver@...dia.com>,
 Prashant Gaikwad <pgaikwad@...dia.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>,
 "Rafael J. Wysocki" <rafael@...nel.org>,
 Viresh Kumar <viresh.kumar@...aro.org>,
 Philipp Zabel <p.zabel@...gutronix.de>, linux-tegra@...r.kernel.org,
 linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-pm@...r.kernel.org
Subject: Re: [PATCH v1 3/3] ARM: tegra: Add DFLL clock support on Tegra 4



25 серпня 2025 р. 07:20:10 GMT+03:00, Mikko Perttunen <mperttunen@...dia.com> пише:
>On Friday, August 22, 2025 2:19 PM Svyatoslav Ryhel wrote:
>> пт, 22 серп. 2025 р. о 06:05 Mikko Perttunen <mperttunen@...dia.com> пише:
>> > On Friday, March 21, 2025 6:55 PM Svyatoslav Ryhel wrote:
>> > > Add DFLL clock node to common Tegra114 device tree along with clocks
>> > > property to cpu node.
>> > > 
>> > > Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
>> > > ---
>> > > 
>> > >  arch/arm/boot/dts/nvidia/tegra114.dtsi | 34 ++++++++++++++++++++++++++
>> > >  1 file changed, 34 insertions(+)
>> > > 
>> > > diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > b/arch/arm/boot/dts/nvidia/tegra114.dtsi index
>> > > 341ec0962460..25d063a47ca5
>> > > 100644
>> > > --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi
>> > > @@ -4,6 +4,7 @@
>> > > 
>> > >  #include <dt-bindings/memory/tegra114-mc.h>
>> > >  #include <dt-bindings/pinctrl/pinctrl-tegra.h>
>> > >  #include <dt-bindings/interrupt-controller/arm-gic.h>
>> > > 
>> > > +#include <dt-bindings/reset/tegra114-car.h>
>> > > 
>> > >  #include <dt-bindings/soc/tegra-pmc.h>
>> > >  
>> > >  #include "tegra114-peripherals-opp.dtsi"
>> > > 
>> > > @@ -710,6 +711,30 @@ mipi: mipi@...e3000 {
>> > > 
>> > >               #nvidia,mipi-calibrate-cells = <1>;
>> > >       
>> > >       };
>> > > 
>> > > +     dfll: clock@...10000 {
>> > > +             compatible = "nvidia,tegra114-dfll";
>> > > +             reg = <0x70110000 0x100>, /* DFLL control */
>> > > +                   <0x70110000 0x100>, /* I2C output control */
>> > > +                   <0x70110100 0x100>, /* Integrated I2C controller */
>> > > +                   <0x70110200 0x100>; /* Look-up table RAM */
>> > > +             interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> > > +             clocks = <&tegra_car TEGRA114_CLK_DFLL_SOC>,
>> > > +                      <&tegra_car TEGRA114_CLK_DFLL_REF>,
>> > > +                      <&tegra_car TEGRA114_CLK_I2C5>;
>> > > +             clock-names = "soc", "ref", "i2c";
>> > > +             resets = <&tegra_car TEGRA114_RST_DFLL_DVCO>;
>> > > +             reset-names = "dvco";
>> > > +             #clock-cells = <0>;
>> > > +             clock-output-names = "dfllCPU_out";
>> > > +             nvidia,sample-rate = <11500>;
>> > 
>> > Should this be 12500? That would match Tegra124 and a downstream kernel
>> > for
>> > Tegra114 I have.
>> 
>> I referred to tegratab and macallan boards in 3.4 kernel which give
>> 11500, maybe sample-rate was changed to 12500 later with tegra124
>> addition?
>
>That's interesting. I was looking at the public roth (Shield Portable) kernel, 
>which does not support Tegra124. I checked the L4T r17 release now, and it 
>seems it's a newer version, where the sample rate has been changed to 11500 on 
>some boards due to a voltage undershoot issue with vdd_cpu on macallan/
>tegratab [1].
>
>So on macallan/tegratab, the vdd_cpu (smps123) ramp rate should be set to 
>2.5mV/us and sample-rate to 11500, while on other boards it can be 5mV/us with 
>12500 for faster ramping.
>
>[1] https://nv-tegra.nvidia.com/r/plugins/gitiles/linux-2.6/+/
>b92cab2d4cb6379aeded80adc4c5d0708c3f038e%5E%21/#F0
>
>Cheers,
>Mikko
>

So should I stick with 11500 as a safer, acceptable for every t114 option?

>> 
>> > > +             nvidia,droop-ctrl = <0x00000f00>;
>> > > +             nvidia,force-mode = <1>;
>> > > +             nvidia,cf = <10>;
>> > > +             nvidia,ci = <0>;
>> > > +             nvidia,cg = <2>;
>> > > +             status = "disabled";
>> > > +     };
>> > > +
>> > > 
>> > >       mmc@...00000 {
>> > >       
>> > >               compatible = "nvidia,tegra114-sdhci";
>> > >               reg = <0x78000000 0x200>;
>> > > 
>> > > @@ -841,6 +866,15 @@ cpu@0 {
>> > > 
>> > >                       device_type = "cpu";
>> > >                       compatible = "arm,cortex-a15";
>> > >                       reg = <0>;
>> > > 
>> > > +
>> > > +                     clocks = <&tegra_car TEGRA114_CLK_CCLK_G>,
>> > > +                              <&tegra_car TEGRA114_CLK_CCLK_LP>,
>> > > +                              <&tegra_car TEGRA114_CLK_PLL_X>,
>> > > +                              <&tegra_car TEGRA114_CLK_PLL_P>,
>> > > +                              <&dfll>;
>> > > +                     clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p",
>> > 
>> > "dfll";
>> > 
>> > > +                     /* FIXME: what's the actual transition time? */
>> > > +                     clock-latency = <300000>;
>> > > 
>> > >               };
>> > >               
>> > >               cpu@1 {
>
>
>
>