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Message-ID: <513ad54017eb96a55176d232ce1464ff51bf452f.camel@siemens.com>
Date: Mon, 25 Aug 2025 13:41:05 +0000
From: "Sverdlin, Alexander" <alexander.sverdlin@...mens.com>
To: "Balamanikandan.Gunasundar@...rochip.com"
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Subject: Re: [PATCH v2] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup
timing
Hi Alexander,
On Mon, 2025-08-25 at 15:22 +0200, Alexander Dahl wrote:
> > > Threw this on top of 6.12.39-rt11 and tested on two custom platforms
> > > both with a Spansion S34ML02G1 SLC 2GBit flash chip, but with
> > > different SoCs (sama5d2, sam9x60). We had difficulties with the
^^^^^^^^^^^^^^^^^^^
[*]
> > > timing of those NAND flash chips in the past and I wanted to make sure
> > > this patch does not break our setup. Seems fine in a quick test,
> > > reading and writing and reading back is successful.
> >
> > thank you for your feedback!
> >
> > Do you see an opportunity to drop the downstream timing quirks with my patch?
>
> Which downstream do you refer to?
That's how I understood the phrase above, that some adjustments are still required
on your side additionally to standard timings. Sorry for the confusion, if it turns
out to be a misunderstanding on my side!
--
Alexander Sverdlin
Siemens AG
www.siemens.com
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