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Message-ID: <aK3k0REdrXJytXAm@lizhi-Precision-Tower-5810>
Date: Tue, 26 Aug 2025 12:46:09 -0400
From: Frank Li <Frank.li@....com>
To: Dan Carpenter <dan.carpenter@...aro.org>
Cc: Chester Lin <chester62515@...il.com>,
Matthias Brugger <mbrugger@...e.com>,
Ghennadi Procopciuc <ghennadi.procopciuc@....nxp.com>,
NXP S32 Linux Team <s32@....com>, Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <s.hauer@...gutronix.de>,
Pengutronix Kernel Team <kernel@...gutronix.de>,
Fabio Estevam <festevam@...il.com>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
linux-arm-kernel@...ts.infradead.org, imx@...ts.linux.dev,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linaro-s32@...aro.org
Subject: Re: [PATCH V2 3/3] arm64: dts: s32g: Add device tree information for
the OCOTP driver
On Tue, Aug 26, 2025 at 07:38:15PM +0300, Dan Carpenter wrote:
> Add the device tree information for the S32G On Chip One-Time
> Programmable Controller (OCOTP) chip.
>
> Signed-off-by: Dan Carpenter <dan.carpenter@...aro.org>
> ---
> v2: change "ocotp: ocotp@...a4000 {" to "ocotp: nvmem@...a4000 {"
>
> arch/arm64/boot/dts/freescale/s32g2.dtsi | 7 +++++++
> arch/arm64/boot/dts/freescale/s32g3.dtsi | 7 +++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> index 6a7cc7b33754..e8cfddabfc24 100644
> --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
> @@ -701,5 +701,12 @@ gic: interrupt-controller@...00000 {
> interrupt-controller;
> #interrupt-cells = <3>;
> };
> +
> + ocotp: nvmem@...a4000 {
> + compatible = "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
Please keep order according to address, 0x400a4000 < 0x50800000
Frank Li
> };
> };
> diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> index 61ee08f0cfdc..8fe1fa35e9ac 100644
> --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi
> @@ -765,6 +765,13 @@ gic: interrupt-controller@...00000 {
> <0x50420000 0x2000>;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> };
> +
> + ocotp: nvmem@...a4000 {
> + compatible = "nxp,s32g3-ocotp", "nxp,s32g2-ocotp";
> + reg = <0x400a4000 0x400>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + };
> };
>
> timer {
> --
> 2.47.2
>
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