linux-kernel - [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD

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Message-ID: <20250827013539.903682-11-terry.bowman@amd.com>
Date: Tue, 26 Aug 2025 20:35:25 -0500
From: Terry Bowman <terry.bowman@....com>
To: <dave@...olabs.net>, <jonathan.cameron@...wei.com>,
	<dave.jiang@...el.com>, <alison.schofield@...el.com>,
	<dan.j.williams@...el.com>, <bhelgaas@...gle.com>, <shiju.jose@...wei.com>,
	<ming.li@...omail.com>, <Smita.KoralahalliChannabasappa@....com>,
	<rrichter@....com>, <dan.carpenter@...aro.org>,
	<PradeepVineshReddy.Kodamati@....com>, <lukas@...ner.de>,
	<Benjamin.Cheatham@....com>, <sathyanarayanan.kuppuswamy@...ux.intel.com>,
	<linux-cxl@...r.kernel.org>, <alucerop@....com>, <ira.weiny@...el.com>
CC: <linux-kernel@...r.kernel.org>, <linux-pci@...r.kernel.org>
Subject: [PATCH v11 10/23] CXL/AER: Update PCI class code check to use FIELD_GET()

Update the AER driver's is_cxl_mem_dev() to use FIELD_GET() while checking
for a CXL Endpoint class code.

Introduce a genmask bitmask for checking PCI class codes and locate in
include/uapi/linux/pci_regs.h.

Update the function documentation to reference the latest CXL
specification.

Signed-off-by: Terry Bowman <terry.bowman@....com>

---
Changes in v10->v11:
- Add #include <linux/bitfield.h> to cxl_ras.c
- Removed line wrapping at "(CXL 3.2, 8.1.12.1)".
---
 drivers/pci/pcie/aer.c        | 1 +
 drivers/pci/pcie/rch_aer.c    | 6 +++---
 include/uapi/linux/pci_regs.h | 2 ++
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c
index 1b5f5b0cdc4f..ed1de9256898 100644
--- a/drivers/pci/pcie/aer.c
+++ b/drivers/pci/pcie/aer.c
@@ -30,6 +30,7 @@
 #include <linux/kfifo.h>
 #include <linux/ratelimit.h>
 #include <linux/slab.h>
+#include <linux/bitfield.h>
 #include <acpi/apei.h>
 #include <acpi/ghes.h>
 #include <ras/ras_event.h>
diff --git a/drivers/pci/pcie/rch_aer.c b/drivers/pci/pcie/rch_aer.c
index bfe071eebf67..c3e2d4cbe8cc 100644
--- a/drivers/pci/pcie/rch_aer.c
+++ b/drivers/pci/pcie/rch_aer.c
@@ -17,10 +17,10 @@ static bool is_cxl_mem_dev(struct pci_dev *dev)
 		return false;
 
 	/*
-	 * CXL Memory Devices must have the 502h class code set (CXL
-	 * 3.0, 8.1.12.1).
+	 * CXL Memory Devices must have the 502h class code set
+	 * (CXL 3.2, 8.1.12.1).
 	 */
-	if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL)
+	if (FIELD_GET(PCI_CLASS_CODE_MASK, dev->class) != PCI_CLASS_MEMORY_CXL)
 		return false;
 
 	return true;
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 252c06402b13..c7b635f6cf36 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -73,6 +73,8 @@
 #define PCI_CLASS_PROG		0x09	/* Reg. Level Programming Interface */
 #define PCI_CLASS_DEVICE	0x0a	/* Device class */
 
+#define PCI_CLASS_CODE_MASK     __GENMASK(23, 8)
+
 #define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
 #define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
 #define PCI_HEADER_TYPE		0x0e	/* 8 bits */
-- 
2.51.0.rc2.21.ge5ab6b3e5a