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Message-Id: <cover.1756344464.git.unicorn_wang@outlook.com>
Date: Thu, 28 Aug 2025 10:15:58 +0800
From: Chen Wang <unicornxw@...il.com>
To: kwilczynski@...nel.org,
	u.kleine-koenig@...libre.com,
	aou@...s.berkeley.edu,
	alex@...ti.fr,
	arnd@...db.de,
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	unicorn_wang@...look.com,
	conor+dt@...nel.org,
	18255117159@....com,
	inochiama@...il.com,
	kishon@...nel.org,
	krzk+dt@...nel.org,
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	s-vadapalli@...com,
	tglx@...utronix.de,
	thomas.richard@...tlin.com,
	sycamoremoon376@...il.com,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org,
	linux-riscv@...ts.infradead.org,
	sophgo@...ts.linux.dev,
	rabenda.cn@...il.com,
	chao.wei@...hgo.com,
	xiaoguang.xing@...hgo.com,
	fengchun.li@...hgo.com
Subject: [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC

From: Chen Wang <unicorn_wang@...look.com>

Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.

This is a completely rewritten PCIe driver for SG2042. It inherits
some previously submitted patch codes (not merged into the upstream
mainline), but the biggest difference is that the support for
compatibility with old 32-bit PCIe devices has been removed in this
new version. This is because after discussing with community users,
we felt that there was not much demand for support for old devices,
so we made a new design based on the simplified design and practical
needs. If someone really needs to play with old devices, we can provide
them with some necessary hack patches in the downstream repository.

Since the new design is quite different from the old code, I will
release it as a new patch series. The old patch series can be found in
here [old-series].

Note, regarding [2/5] of this patchset, this fix is introduced because
the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not
a must-have parameter, if we use it w/o checking will cause a null
pointer access error during runtime.

Link: https://lore.kernel.org/linux-riscv/cover.1736923025.git.unicorn_wang@outlook.com/ [old-series]

This patchset is based on v6.17-rc1.

Thanks,
Chen

---

Chen Wang (5):
  dt-bindings: pci: Add Sophgo SG2042 PCIe host
  PCI: cadence: Fix NULL pointer error for ops
  PCI: sg2042: Add Sophgo SG2042 PCIe driver
  riscv: sophgo: dts: add pcie controllers for SG2042
  riscv: sophgo: dts: enable pcie for PioneerBox

 .../bindings/pci/sophgo,sg2042-pcie-host.yaml |  66 +++++++++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |  12 ++
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  66 +++++++++
 drivers/pci/controller/cadence/Kconfig        |  12 ++
 drivers/pci/controller/cadence/Makefile       |   1 +
 .../controller/cadence/pcie-cadence-host.c    |   2 +-
 drivers/pci/controller/cadence/pcie-cadence.c |   4 +-
 drivers/pci/controller/cadence/pcie-cadence.h |   6 +-
 drivers/pci/controller/cadence/pcie-sg2042.c  | 134 ++++++++++++++++++
 9 files changed, 297 insertions(+), 6 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
 create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c


base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585
-- 
2.34.1


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