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Message-ID: <fe7afeb5-e009-4f68-a3a8-58ff967d3780@tuxon.dev>
Date: Thu, 28 Aug 2025 22:11:55 +0300
From: claudiu beznea <claudiu.beznea@...on.dev>
To: Bjorn Helgaas <helgaas@...nel.org>
Cc: bhelgaas@...gle.com, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
geert+renesas@...der.be, magnus.damm@...il.com, catalin.marinas@....com,
will@...nel.org, mturquette@...libre.com, sboyd@...nel.org,
p.zabel@...gutronix.de, lizhi.hou@....com, linux-pci@...r.kernel.org,
linux-renesas-soc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-clk@...r.kernel.org, Claudiu Beznea
<claudiu.beznea.uj@...renesas.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>
Subject: Re: [PATCH v3 4/9] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add
documentation for the PCIe IP on Renesas RZ/G3S
Hi, Bjorn,
On 8/8/25 14:25, Claudiu Beznea wrote:
> Hi, Bjorn,
>
> On 08.07.2025 19:34, Bjorn Helgaas wrote:
>> On Fri, Jul 04, 2025 at 07:14:04PM +0300, Claudiu wrote:
>>> From: Claudiu Beznea <claudiu.beznea.uj@...renesas.com>
>>>
>>> The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express
>>> Base Specification 4.0. It is designed for root complex applications and
>>> features a single-lane (x1) implementation. Add documentation for it.
>>
>>> +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml
>>
>> The "r9a08g045s33" in the filename seems oddly specific. Does it
>> leave room for descendants of the current chip that will inevitably be
>> added in the future? Most bindings are named with a fairly generic
>> family name, e.g., "fsl,layerscape", "hisilicon,kirin", "intel,
>> keembay", "samsung,exynos", etc.
>>
>>> +examples:
>>> + - |
>>> + #include <dt-bindings/clock/r9a08g045-cpg.h>
>>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +
>>> + bus {
>>> + #address-cells = <2>;
>>> + #size-cells = <2>;
>>> +
>>> + pcie@...40000 {
>>> + compatible = "renesas,r9a08g045s33-pcie";
>>> + reg = <0 0x11e40000 0 0x10000>;
>>> + ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>;
>>> + dma-ranges = <0x42000000 0 0x48000000 0 0x48000000 0 0x38000000>;
>>> + bus-range = <0x0 0xff>;
>>> + clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
>>> + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
>>> + clock-names = "aclk", "pm";
>>> + resets = <&cpg R9A08G045_PCI_ARESETN>,
>>> + <&cpg R9A08G045_PCI_RST_B>,
>>> + <&cpg R9A08G045_PCI_RST_GP_B>,
>>> + <&cpg R9A08G045_PCI_RST_PS_B>,
>>> + <&cpg R9A08G045_PCI_RST_RSM_B>,
>>> + <&cpg R9A08G045_PCI_RST_CFG_B>,
>>> + <&cpg R9A08G045_PCI_RST_LOAD_B>;
>>> + reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
>>> + "rst_rsm_b", "rst_cfg_b", "rst_load_b";
>>> + interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
>>> + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
>>> + interrupt-names = "serr", "serr_cor", "serr_nonfatal",
>>> + "serr_fatal", "axi_err", "inta",
>>> + "intb", "intc", "intd", "msi",
>>> + "link_bandwidth", "pm_pme", "dma",
>>> + "pcie_evt", "msg", "all";
>>> + #interrupt-cells = <1>;
>>> + interrupt-controller;
>>> + interrupt-map-mask = <0 0 0 7>;
>>> + interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INT A */
>>> + <0 0 0 2 &pcie 0 0 0 1>, /* INT B */
>>> + <0 0 0 3 &pcie 0 0 0 2>, /* INT C */
>>> + <0 0 0 4 &pcie 0 0 0 3>; /* INT D */
>>
>> The spec styles these closed up: "INTA", "INTB", etc.
>
> I'll update it.
>
>>
>>> + device_type = "pci";
>>> + num-lanes = <1>;
>>> + #address-cells = <3>;
>>> + #size-cells = <2>;
>>> + power-domains = <&cpg>;
>>> + vendor-id = <0x1912>;
>>> + device-id = <0x0033>;
>>
>> Some of this is specific to a Root Port, not to the Root Complex as a
>> whole. E.g., device-type = "pci", num-lanes, vendor-id, device-id,
>> are Root Port properties. Some of the resets, clocks, and interrupts
>> might be as well.
>>
>> I really want to separate those out because even though this
>> particular version of this PCIe controller only supports a single Root
>> Port, there are other controllers (and possibly future iterations of
>> this controller) that support multiple Root Ports, and it makes
>> maintenance easier if the DT bindings and the driver structures are
>> similar.
>
> I'll ask the Renesas HW team about the resets and clocks as the HW manual
> don't offer any information about this.
Renesas HW team replied to me that there are no clock, reset, or interrupt
signals dedicated specifically to the Root Port. All these signals are shared
across the PCIe system.
Taking this and your suggestions into account, I have prepared the following
device tree:
pcie: pcie@...40000 {
compatible = "renesas,r9a08g045-pcie";
reg = <0 0x11e40000 0 0x10000>;
ranges = <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>;
/* Map all possible DRAM ranges (4 GB). */
dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0x1 0x0>;
bus-range = <0x0 0xff>;
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "serr", "serr_cor", "serr_nonfatal",
"serr_fatal", "axi_err", "inta",
"intb", "intc", "intd", "msi",
"link_bandwidth", "pm_pme", "dma",
"pcie_evt", "msg", "all";
#interrupt-cells = <1>;
interrupt-controller;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie 0 0 0 0>, /* INTA */
<0 0 0 2 &pcie 0 0 0 1>, /* INTB */
<0 0 0 3 &pcie 0 0 0 2>, /* INTC */
<0 0 0 4 &pcie 0 0 0 3>; /* INTD */
clocks = <&cpg CPG_MOD R9A08G045_PCI_ACLK>,
<&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>;
clock-names = "aclk", "pm";
resets = <&cpg R9A08G045_PCI_ARESETN>,
<&cpg R9A08G045_PCI_RST_B>,
<&cpg R9A08G045_PCI_RST_GP_B>,
<&cpg R9A08G045_PCI_RST_PS_B>,
<&cpg R9A08G045_PCI_RST_RSM_B>,
<&cpg R9A08G045_PCI_RST_CFG_B>,
<&cpg R9A08G045_PCI_RST_LOAD_B>;
reset-names = "aresetn", "rst_b", "rst_gp_b", "rst_ps_b",
"rst_rsm_b", "rst_cfg_b", "rst_load_b";
power-domains = <&cpg>;
device_type = "pci";
#address-cells = <3>;
#size-cells = <2>;
renesas,sysc = <&sysc>;
status = "disabled";
pcie_port0: pcie@0,0 {
reg = <0x0 0x0 0x0 0x0 0x0>;
ranges;
clocks = <&versa3 5>;
clock-names = "ref";
device_type = "pci";
vendor-id = <0x1912>;
device-id = <0x0033>;
bus-range = <0x1 0xff>;
#address-cells = <3>;
#size-cells = <2>;
};
};
and added clocks in the port section, populated with the reference clock that is
provided by a board specific clock generator (that I failed to noticed
previously on schematics; this clock is always on).
Please let me know if you find something wrong with this format.
Thank you,
Claudiu
>
> If they will confirm some of the clocks and/or resets could be controlled
> as part of a port then patch 3/9 "PCI: of_property: Restore the arguments
> of the next level parent" in this series will not be needed anymore. Would
> you prefer me to abandon it or post it as individual patch, if any?
>
>>
>> This email includes pointers to sample DT bindings and driver code
>> that is structured to allow multiple Root Ports:
>>
>> https://lore.kernel.org/linux-pci/20250625221653.GA1590146@bhelgaas/
>
> Thank you for this!
>
> And, thank you for your review,
> Claudiu
>
>>
>> Bjorn
>
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