| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250828080855.3502514-14-paul-pl.chen@mediatek.com>
Date: Thu, 28 Aug 2025 16:07:08 +0800
From: Paul Chen <paul-pl.chen@...iatek.com>
To: <robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<chunkuang.hu@...nel.org>, <angelogioacchino.delregno@...labora.com>
CC: <matthias.bgg@...il.com>, <p.zabel@...gutronix.de>,
<jason-jh.lin@...iatek.com>, <nancy.lin@...iatek.com>,
<singo.chang@...iatek.com>, <xiandong.wang@...iatek.com>,
<sirius.wang@...iatek.com>, <paul-pl.chen@...iatek.com>,
<sunny.shen@...iatek.com>, <fshao@...omium.org>, <treapking@...omium.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<dri-devel@...ts.freedesktop.org>, <linux-mediatek@...ts.infradead.org>,
<linux-arm-kernel@...ts.infradead.org>,
<Project_Global_Chrome_Upstream_Group@...iatek.com>
Subject: [PATCH v4 13/19] drm/mediatek: Export OVL Blend function
From: Paul-pl Chen <paul-pl.chen@...iatek.com>
For the new BLENDER component, the OVL ignore pixel alpha logic
should be exported as a function and reused it.
Signed-off-by: Nancy Lin <nancy.lin@...iatek.com>
Signed-off-by: Paul-pl Chen <paul-pl.chen@...iatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 68 +++++++++++++++++--------
drivers/gpu/drm/mediatek/mtk_disp_ovl.h | 8 +++
2 files changed, 56 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index e3ee3f60f4ba..7cd3978beb98 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -228,6 +228,23 @@ void mtk_ovl_disable_vblank(struct device *dev)
writel_relaxed(0x0, ovl->regs + DISP_REG_OVL_INTEN);
}
+bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode)
+{
+ if (!state->base.fb)
+ return false;
+
+ /*
+ * Although the alpha channel can be ignored, CONST_BLD must be enabled
+ * for XRGB format, otherwise OVL will still read the value from memory.
+ * For RGB888 related formats, whether CONST_BLD is enabled or not won't
+ * affect the result. Therefore we use !has_alpha as the condition.
+ */
+ if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)
+ return true;
+
+ return false;
+}
+
u32 mtk_ovl_get_blend_modes(struct device *dev)
{
struct mtk_disp_ovl *ovl = dev_get_drvdata(dev);
@@ -414,6 +431,29 @@ void mtk_ovl_layer_off(struct device *dev, unsigned int idx,
DISP_REG_OVL_RDMA_CTRL(idx));
}
+unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes)
+{
+ unsigned int blend_mode = DRM_MODE_BLEND_COVERAGE;
+
+ /*
+ * For the platforms where OVL_CON_CLRFMT_MAN is defined in the hardware data sheet
+ * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB888
+ * and supports premultiplied color formats, such as OVL_CON_CLRFMT_PARGB8888.
+ *
+ * Check blend_modes in the driver data to see if premultiplied mode is supported.
+ * If not, use coverage mode instead to set it to the supported color formats.
+ *
+ * Current DRM assumption is that alpha is default premultiplied, so the bitmask of
+ * blend_modes must include BIT(DRM_MODE_BLEND_PREMULTI). Otherwise, mtk_plane_init()
+ * will get an error return from drm_plane_create_blend_mode_property() and
+ * state->base.pixel_blend_mode should not be used.
+ */
+ if (blend_modes & BIT(DRM_MODE_BLEND_PREMULTI))
+ blend_mode = state->base.pixel_blend_mode;
+
+ return blend_mode;
+}
+
unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
bool fmt_rgb565_is_0, bool color_convert,
u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap)
@@ -541,7 +581,7 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
unsigned int rotation = pending->rotation;
unsigned int offset = (pending->y << 16) | pending->x;
unsigned int src_size = (pending->height << 16) | pending->width;
- unsigned int blend_mode = state->base.pixel_blend_mode;
+ unsigned int blend_mode = mtk_ovl_get_blend_mode(state, ovl->data->blend_modes);
unsigned int ignore_pixel_alpha = 0;
unsigned int con;
@@ -566,17 +606,8 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
* For blend_modes supported SoCs, always enable alpha blending.
* For blend_modes unsupported SoCs, enable alpha blending when has_alpha is set.
*/
- if (blend_mode || state->base.fb->format->has_alpha)
+ if (state->base.pixel_blend_mode || state->base.fb->format->has_alpha)
con |= OVL_CON_AEN;
-
- /*
- * Although the alpha channel can be ignored, CONST_BLD must be enabled
- * for XRGB format, otherwise OVL will still read the value from memory.
- * For RGB888 related formats, whether CONST_BLD is enabled or not won't
- * affect the result. Therefore we use !has_alpha as the condition.
- */
- if (blend_mode == DRM_MODE_BLEND_PIXEL_NONE || !state->base.fb->format->has_alpha)
- ignore_pixel_alpha = OVL_CONST_BLEND;
}
/*
@@ -602,6 +633,9 @@ void mtk_ovl_layer_config(struct device *dev, unsigned int idx,
mtk_ddp_write_relaxed(cmdq_pkt, con, &ovl->cmdq_reg, ovl->regs,
DISP_REG_OVL_CON(idx));
+
+ if (mtk_ovl_is_ignore_pixel_alpha(state, blend_mode))
+ ignore_pixel_alpha = OVL_CONST_BLEND;
mtk_ddp_write_relaxed(cmdq_pkt, pitch_lsb | ignore_pixel_alpha,
&ovl->cmdq_reg, ovl->regs, DISP_REG_OVL_PITCH(idx));
mtk_ddp_write_relaxed(cmdq_pkt, src_size, &ovl->cmdq_reg, ovl->regs,
@@ -751,9 +785,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_driver_data = {
.layer_nr = 4,
.fmt_rgb565_is_0 = true,
.smi_id_en = true,
- .blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE) |
- BIT(DRM_MODE_BLEND_PIXEL_NONE),
+ .blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
.formats = mt8173_ovl_formats,
.num_formats = mt8173_ovl_formats_len,
};
@@ -764,9 +796,7 @@ static const struct mtk_disp_ovl_data mt8192_ovl_2l_driver_data = {
.layer_nr = 2,
.fmt_rgb565_is_0 = true,
.smi_id_en = true,
- .blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE) |
- BIT(DRM_MODE_BLEND_PIXEL_NONE),
+ .blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
.formats = mt8173_ovl_formats,
.num_formats = mt8173_ovl_formats_len,
};
@@ -778,9 +808,7 @@ static const struct mtk_disp_ovl_data mt8195_ovl_driver_data = {
.fmt_rgb565_is_0 = true,
.smi_id_en = true,
.supports_afbc = true,
- .blend_modes = BIT(DRM_MODE_BLEND_PREMULTI) |
- BIT(DRM_MODE_BLEND_COVERAGE) |
- BIT(DRM_MODE_BLEND_PIXEL_NONE),
+ .blend_modes = MTK_OVL_SUPPORT_BLEND_MODES,
.formats = mt8195_ovl_formats,
.num_formats = mt8195_ovl_formats_len,
.supports_clrfmt_ext = true,
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
index 4f446d2e0712..431567538eb5 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.h
@@ -6,14 +6,22 @@
#ifndef __MTK_DISP_OVL_H__
#define __MTK_DISP_OVL_H__
+#include <drm/drm_blend.h>
#include <drm/drm_fourcc.h>
+#define MTK_OVL_SUPPORT_BLEND_MODES \
+ (BIT(DRM_MODE_BLEND_PREMULTI) | \
+ BIT(DRM_MODE_BLEND_COVERAGE) | \
+ BIT(DRM_MODE_BLEND_PIXEL_NONE))
+
extern const u32 mt8173_ovl_formats[];
extern const size_t mt8173_ovl_formats_len;
extern const u32 mt8195_ovl_formats[];
extern const size_t mt8195_ovl_formats_len;
bool mtk_ovl_is_10bit_rgb(unsigned int fmt);
+bool mtk_ovl_is_ignore_pixel_alpha(struct mtk_plane_state *state, unsigned int blend_mode);
+unsigned int mtk_ovl_get_blend_mode(struct mtk_plane_state *state, unsigned int blend_modes);
unsigned int mtk_ovl_fmt_convert(unsigned int fmt, unsigned int blend_mode,
bool fmt_rgb565_is_0, bool color_convert,
u8 clrfmt_shift, u32 clrfmt_man, u32 byte_swap, u32 rgb_swap);
--
2.45.2
Powered by blists - more mailing lists