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Message-ID: <20250828083926.16849-1-inbaraj.e@samsung.com>
Date: Thu, 28 Aug 2025 14:09:26 +0530
From: Inbaraj E <inbaraj.e@...sung.com>
To: alim.akhtar@...sung.com, linux-fsd@...la.com, krzk@...nel.org,
robh@...nel.org, conor+dt@...nel.org
Cc: linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
pankaj.dubey@...sung.com, ravi.patel@...sung.com, shradha.t@...sung.com,
Inbaraj E <inbaraj.e@...sung.com>
Subject: [v3] arm64: dts: fsd: Add CSIS nodes
The Tesla FSD SoC CSIS IP bundles MIPI CSI-2 link controller and video
capture interface. Add nodes describing the MIPI CSI-2 link controller
and video capture interface.
Signed-off-by: Inbaraj E <inbaraj.e@...sung.com>
---
Changes since v2:
- Changed generic node name
- Fixed node ordering
Here is patch link for v2:
https://lore.kernel.org/linux-media/20250814140943.22531-1-inbaraj.e@samsung.com/
This patch is dependent on below patchset
https://lore.kernel.org/linux-media/20250822002734.23516-1-laurent.pinchart@ideasonboard.com/T/#t
arch/arm64/boot/dts/tesla/fsd.dtsi | 540 +++++++++++++++++++++++++++++
1 file changed, 540 insertions(+)
diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi
index a5ebb3f9b18f..22afcf5a5dda 100644
--- a/arch/arm64/boot/dts/tesla/fsd.dtsi
+++ b/arch/arm64/boot/dts/tesla/fsd.dtsi
@@ -485,6 +485,546 @@ sysreg_cam: system-controller@...30000 {
reg = <0x0 0x12630000 0x0 0x500>;
};
+ mipicsi0: csi@...40000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12640000 0x0 0x124>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_0_out: endpoint {
+ remote-endpoint = <&csis_in_0>;
+ };
+ };
+ };
+ };
+
+ csis0: csis@...41000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12641000 0x0 0x44c>;
+ interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_0_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_0: endpoint {
+ remote-endpoint = <&mipi_csis_0_out>;
+ };
+ };
+ };
+
+ mipicsi1: csi@...50000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12650000 0x0 0x124>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_1_out: endpoint {
+ remote-endpoint = <&csis_in_1>;
+ };
+ };
+ };
+ };
+
+ csis1: csis@...51000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12651000 0x0 0x44c>;
+ interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_1_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_1: endpoint {
+ remote-endpoint = <&mipi_csis_1_out>;
+ };
+ };
+ };
+
+ mipicsi2: csi@...60000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12660000 0x0 0x124>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_2_out: endpoint {
+ remote-endpoint = <&csis_in_2>;
+ };
+ };
+ };
+ };
+
+ csis2: csis@...61000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12661000 0x0 0x44c>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_2_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_2: endpoint {
+ remote-endpoint = <&mipi_csis_2_out>;
+ };
+ };
+ };
+
+ mipicsi3: csi@...70000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12670000 0x0 0x124>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_3_out: endpoint {
+ remote-endpoint = <&csis_in_3>;
+ };
+ };
+ };
+ };
+
+ csis3: csis@...71000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12671000 0x0 0x44c>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI0_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI0_3_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_3: endpoint {
+ remote-endpoint = <&mipi_csis_3_out>;
+ };
+ };
+ };
+
+ mipicsi4: csi@...80000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12680000 0x0 0x124>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_4_out: endpoint {
+ remote-endpoint = <&csis_in_4>;
+ };
+ };
+ };
+ };
+
+ csis4: csis@...81000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12681000 0x0 0x44c>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_0_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_4: endpoint {
+ remote-endpoint = <&mipi_csis_4_out>;
+ };
+ };
+ };
+
+ mipicsi5: csi@...90000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x12690000 0x0 0x124>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_5_out: endpoint {
+ remote-endpoint = <&csis_in_5>;
+ };
+ };
+ };
+ };
+
+ csis5: csis@...91000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x12691000 0x0 0x44c>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_1_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_5: endpoint {
+ remote-endpoint = <&mipi_csis_5_out>;
+ };
+ };
+ };
+
+ mipicsi6: csi@...a0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126a0000 0x0 0x124>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_6_out: endpoint {
+ remote-endpoint = <&csis_in_6>;
+ };
+ };
+ };
+ };
+
+ csis6: csis@...a1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126a1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_2_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_6: endpoint {
+ remote-endpoint = <&mipi_csis_6_out>;
+ };
+ };
+ };
+
+ mipicsi7: csi@...b0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126b0000 0x0 0x124>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_7_out: endpoint {
+ remote-endpoint = <&csis_in_7>;
+ };
+ };
+ };
+ };
+
+ csis7: csis@...b1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126b1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI1_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI1_3_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_7: endpoint {
+ remote-endpoint = <&mipi_csis_7_out>;
+ };
+ };
+ };
+
+ mipicsi8: csi@...c0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126c0000 0x0 0x124>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_8_out: endpoint {
+ remote-endpoint = <&csis_in_8>;
+ };
+ };
+ };
+ };
+
+ csis8: csis@...c1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126c1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_0_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_0_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_8: endpoint {
+ remote-endpoint = <&mipi_csis_8_out>;
+ };
+ };
+ };
+
+ mipicsi9: csi@...d0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126d0000 0x0 0x124>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_9_out: endpoint {
+ remote-endpoint = <&csis_in_9>;
+ };
+ };
+ };
+ };
+
+ csis9: csis@...d1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126d1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_1_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_1_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_9: endpoint {
+ remote-endpoint = <&mipi_csis_9_out>;
+ };
+ };
+ };
+
+ mipicsi10: csi@...e0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126e0000 0x0 0x124>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_10_out: endpoint {
+ remote-endpoint = <&csis_in_10>;
+ };
+ };
+ };
+ };
+
+ csis10: csis@...e1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126e1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_2_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_2_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_10: endpoint {
+ remote-endpoint = <&mipi_csis_10_out>;
+ };
+ };
+ };
+
+ mipicsi11: csi@...f0000 {
+ compatible = "tesla,fsd-mipi-csi2";
+ reg = <0x0 0x126f0000 0x0 0x124>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>;
+ clock-names = "aclk", "pclk";
+ tesla,syscon-csis = <&sysreg_cam 0x40c>;
+ fsl,num-channels = <4>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_csis_11_out: endpoint {
+ remote-endpoint = <&csis_in_11>;
+ };
+ };
+ };
+ };
+
+ csis11: csis@...f1000 {
+ compatible = "tesla,fsd-csis-media";
+ reg = <0x0 0x126f1000 0x0 0x44c>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clock_csi CAM_CSI2_3_IPCLKPORT_I_ACLK>,
+ <&clock_csi CAM_CSI2_3_IPCLKPORT_I_PCLK>,
+ <&clock_csi CAM_CSI_PLL>;
+ clock-names = "aclk", "pclk", "pll";
+ iommus = <&smmu_isp 0x0 0x0>;
+
+ port {
+ csis_in_11: endpoint {
+ remote-endpoint = <&mipi_csis_11_out>;
+ };
+ };
+ };
+
clock_mfc: clock-controller@...10000 {
compatible = "tesla,fsd-clock-mfc";
reg = <0x0 0x12810000 0x0 0x3000>;
--
2.49.0
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