linux-kernel - Re: [PATCH v3 4/6] net: dsa: lantiq_gswip: support offset of MII registers

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Message-ID: <aLHDHbdBYTLzCMiL@pidgin.makrotopia.org>
Date: Fri, 29 Aug 2025 16:11:25 +0100
From: Daniel Golle <daniel@...rotopia.org>
To: Andrew Lunn <andrew@...n.ch>, Vladimir Oltean <olteanv@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Hauke Mehrtens <hauke@...ke-m.de>,
	Russell King <linux@...linux.org.uk>, linux-kernel@...r.kernel.org,
	netdev@...r.kernel.org
Cc: Andreas Schirm <andreas.schirm@...mens.com>,
	Lukas Stockmann <lukas.stockmann@...mens.com>,
	Alexander Sverdlin <alexander.sverdlin@...mens.com>,
	Peter Christen <peter.christen@...mens.com>,
	Avinash Jayaraman <ajayaraman@...linear.com>,
	Bing tao Xu <bxu@...linear.com>, Liang Xu <lxu@...linear.com>,
	Juraj Povazanec <jpovazanec@...linear.com>,
	"Fanni (Fang-Yi) Chan" <fchan@...linear.com>,
	"Benny (Ying-Tsan) Weng" <yweng@...linear.com>,
	"Livia M. Rosu" <lrosu@...linear.com>,
	John Crispin <john@...ozen.org>
Subject: Re: [PATCH v3 4/6] net: dsa: lantiq_gswip: support offset of MII
 registers

On Fri, Aug 29, 2025 at 02:02:16PM +0100, Daniel Golle wrote:
> The MaxLinear GSW1xx family got a single (R)(G)MII port at index 5 but
> the registers MII_PCDU and MII_CFG are those of port 0.
> Allow applying an offset for the port index to access those registers.
> 
> Signed-off-by: Daniel Golle <daniel@...rotopia.org>
> Reviewed-by: Hauke Mehrtens <hauke@...ke-m.de>
> ---
> v3: no changes
> v2: no changes

I forgot to include the change I made upon Hauke's request, and it's even
wrong. Sorry for the noise. I will send v4 tomorrow...


> @@ -2027,6 +2035,7 @@ static const struct gswip_hw_info gswip_xrx200 = {
>  	.max_ports = 7,
>  	.allowed_cpu_ports = BIT(6),
>  	.mii_ports = BIT(0) | BIT(1) | BIT(5),
> +	.mii_port_reg_offset = 0;
>  	.phylink_get_caps = gswip_xrx200_phylink_get_caps,
>  	.pce_microcode = &gswip_pce_microcode,
>  	.pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode),
> @@ -2037,6 +2046,7 @@ static const struct gswip_hw_info gswip_xrx300 = {
>  	.max_ports = 7,
>  	.allowed_cpu_ports = BIT(6),
>  	.mii_ports = BIT(0) | BIT(5),
> +	.mii_port_reg_offset = 0;
>  	.phylink_get_caps = gswip_xrx300_phylink_get_caps,
>  	.pce_microcode = &gswip_pce_microcode,
>  	.pce_microcode_size = ARRAY_SIZE(gswip_pce_microcode),

Both above will triger compiler error, should be ',' instead ';'.