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Message-ID: <20250829170602.000029fd@huawei.com>
Date: Fri, 29 Aug 2025 17:06:02 +0100
From: Jonathan Cameron <jonathan.cameron@...wei.com>
To: Shiju Jose <shiju.jose@...wei.com>
CC: Terry Bowman <terry.bowman@....com>, "dave@...olabs.net"
	<dave@...olabs.net>, "dave.jiang@...el.com" <dave.jiang@...el.com>,
	"alison.schofield@...el.com" <alison.schofield@...el.com>,
	"dan.j.williams@...el.com" <dan.j.williams@...el.com>, "bhelgaas@...gle.com"
	<bhelgaas@...gle.com>, "ming.li@...omail.com" <ming.li@...omail.com>,
	"Smita.KoralahalliChannabasappa@....com"
	<Smita.KoralahalliChannabasappa@....com>, "rrichter@....com"
	<rrichter@....com>, "dan.carpenter@...aro.org" <dan.carpenter@...aro.org>,
	"PradeepVineshReddy.Kodamati@....com" <PradeepVineshReddy.Kodamati@....com>,
	"lukas@...ner.de" <lukas@...ner.de>, "Benjamin.Cheatham@....com"
	<Benjamin.Cheatham@....com>, "sathyanarayanan.kuppuswamy@...ux.intel.com"
	<sathyanarayanan.kuppuswamy@...ux.intel.com>, "linux-cxl@...r.kernel.org"
	<linux-cxl@...r.kernel.org>, "alucerop@....com" <alucerop@....com>,
	"ira.weiny@...el.com" <ira.weiny@...el.com>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>, "linux-pci@...r.kernel.org"
	<linux-pci@...r.kernel.org>
Subject: Re: [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL
 Endpoints and CXL Ports


> >Subject: [PATCH v11 13/23] cxl/pci: Unify CXL trace logging for CXL Endpoints
> >and CXL Ports
> >
> >CXL currently has separate trace routines for CXL Port errors and CXL Endpoint
> >errors. This is inconvenient for the user because they must enable
> >2 sets of trace routines. Make updates to the trace logging such that a single
> >trace routine logs both CXL Endpoint and CXL Port protocol errors.
> >
> >Keep the trace log fields 'memdev' and 'host'. While these are not accurate for
> >non-Endpoints the fields will remain as-is to prevent breaking userspace RAS
> >trace consumers.
> >
> >Add serial number parameter to the trace logging. This is used for EPs and 0 is
> >provided for CXL port devices without a serial number.
> >
> >Leave the correctable and uncorrectable trace routines' TP_STRUCT__entry()
> >unchanged with respect to member data types and order.
> >
> >Below is output of correctable and uncorrectable protocol error logging.
> >CXL Root Port and CXL Endpoint examples are included below.
> >
> >Root Port:
> >cxl_aer_correctable_error: memdev=0000:0c:00.0 host=pci0000:0c serial: 0
> >status='CRC Threshold Hit'
> >cxl_aer_uncorrectable_error: memdev=0000:0c:00.0 host=pci0000:0c serial: 0
> >status: 'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity
> >Error'
> >
> >Endpoint:
> >cxl_aer_correctable_error: memdev=mem3 host=0000:0f:00.0 serial=0
> >status='CRC Threshold Hit'
> >cxl_aer_uncorrectable_error: memdev=mem3 host=0000:0f:00.0 serial: 0 status:
> >'Cache Byte Enable Parity Error' first_error: 'Cache Byte Enable Parity Error'
> >
> >Signed-off-by: Terry Bowman <terry.bowman@....com>  
> 
> Reviewed-by: Shiju Jose <shiju.jose@...wei.com>,
> apart from one error below.
> 
Good spot.
With that fixed up,
Reviewed-by: Jonathan Cameron <jonathan.cameron@...wei.com>

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