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Message-Id: <20250829173254.2068763-12-joelagnelf@nvidia.com>
Date: Fri, 29 Aug 2025 13:32:48 -0400
From: Joel Fernandes <joelagnelf@...dia.com>
To: linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
dakr@...nel.org,
acourbot@...dia.com
Cc: Alistair Popple <apopple@...dia.com>,
Miguel Ojeda <ojeda@...nel.org>,
Alex Gaynor <alex.gaynor@...il.com>,
Boqun Feng <boqun.feng@...il.com>,
Gary Guo <gary@...yguo.net>,
bjorn3_gh@...tonmail.com,
Benno Lossin <lossin@...nel.org>,
Andreas Hindborg <a.hindborg@...nel.org>,
Alice Ryhl <aliceryhl@...gle.com>,
Trevor Gross <tmgross@...ch.edu>,
David Airlie <airlied@...il.com>,
Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
John Hubbard <jhubbard@...dia.com>,
Joel Fernandes <joelagnelf@...dia.com>,
Timur Tabi <ttabi@...dia.com>,
joel@...lfernandes.org,
nouveau@...ts.freedesktop.org,
rust-for-linux@...r.kernel.org
Subject: [PATCH 11/17] nova-core: sequencer: Implement core resume operation
Implement core resume operation. This is the last step of the sequencer
resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP
boot.
Signed-off-by: Joel Fernandes <joelagnelf@...dia.com>
---
drivers/gpu/nova-core/falcon/gsp.rs | 1 -
drivers/gpu/nova-core/gsp/sequencer.rs | 47 ++++++++++++++++++++++++--
drivers/gpu/nova-core/nvfw.rs | 1 -
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon/gsp.rs b/drivers/gpu/nova-core/falcon/gsp.rs
index 58478ada6d3e..c9ab375fd8a1 100644
--- a/drivers/gpu/nova-core/falcon/gsp.rs
+++ b/drivers/gpu/nova-core/falcon/gsp.rs
@@ -35,7 +35,6 @@ pub(crate) fn clear_swgen0_intr(&self, bar: &Bar0) {
}
/// Function to check if GSP reload/resume has completed during the boot process.
- #[expect(dead_code)]
pub(crate) fn check_reload_completed(&self, bar: &Bar0, timeout: Delta) -> Result<bool> {
wait_on(timeout, || {
let val = regs::NV_PGC6_BSI_SECURE_SCRATCH_14::read(bar);
diff --git a/drivers/gpu/nova-core/gsp/sequencer.rs b/drivers/gpu/nova-core/gsp/sequencer.rs
index 826c06041e41..cb21c060e09b 100644
--- a/drivers/gpu/nova-core/gsp/sequencer.rs
+++ b/drivers/gpu/nova-core/gsp/sequencer.rs
@@ -43,6 +43,7 @@ pub(crate) enum GspSeqCmd {
CoreReset,
CoreStart,
CoreWaitForHalt,
+ CoreResume,
}
impl GspSeqCmd {
@@ -71,6 +72,7 @@ pub(crate) fn from_fw_cmd(cmd: &fw::GSP_SEQUENCER_BUFFER_CMD) -> Result<Self> {
fw::GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_WAIT_FOR_HALT => {
Ok(GspSeqCmd::CoreWaitForHalt)
}
+ fw::GSP_SEQ_BUF_OPCODE_GSP_SEQ_BUF_OPCODE_CORE_RESUME => Ok(GspSeqCmd::CoreResume),
_ => Err(EINVAL),
}
}
@@ -93,7 +95,10 @@ pub(crate) fn size_bytes(&self) -> usize {
let opcode_size = size_of::<fw::GSP_SEQ_BUF_OPCODE>();
match self {
// Each simple command type just adds 4 bytes (opcode_size) for the header
- GspSeqCmd::CoreReset | GspSeqCmd::CoreStart | GspSeqCmd::CoreWaitForHalt => opcode_size,
+ GspSeqCmd::CoreReset
+ | GspSeqCmd::CoreStart
+ | GspSeqCmd::CoreWaitForHalt
+ | GspSeqCmd::CoreResume => opcode_size,
// For commands with payloads, add the payload size in bytes
GspSeqCmd::RegWrite(_) => opcode_size + size_of::<fw::GSP_SEQ_BUF_PAYLOAD_REG_WRITE>(),
@@ -107,7 +112,6 @@ pub(crate) fn size_bytes(&self) -> usize {
}
}
-#[expect(dead_code)]
pub(crate) struct GspSequencer<'a> {
pub seq_info: GspSequencerInfo<'a>,
pub bar: &'a Bar0,
@@ -252,6 +256,45 @@ fn run(&self, seq: &GspSequencer<'_>) -> Result {
seq.gsp_falcon.wait_till_halted(seq.bar)?;
Ok(())
}
+ GspSeqCmd::CoreResume => {
+ dev_dbg!(seq.dev, "CoreResume\n");
+ // At this point, 'SEC2-RTOS' has been loaded into SEC2 by the sequencer
+ // but neither SEC2-RTOS nor GSP-RM is running yet. This part of the
+ // sequencer will start both.
+
+ // First prepare the GSP for resume.
+ seq.gsp_falcon.reset(seq.bar)?;
+ seq.gsp_falcon.write_mailboxes(
+ seq.bar,
+ Some(seq.libos_dma_handle as u32),
+ Some((seq.libos_dma_handle >> 32) as u32),
+ )?;
+
+ // Now start the SEC2, this will resume GSP-RM on the GSP.
+ seq.sec2_falcon.start(seq.bar)?;
+
+ // Check if GSP-RM resumed.
+ seq.gsp_falcon
+ .check_reload_completed(seq.bar, Delta::from_secs(2))?;
+
+ // Check for any errors in the SEC2 mailbox registers.
+ let mbox0 = seq.sec2_falcon.read_mailbox0(seq.bar)?;
+ if mbox0 != 0 {
+ dev_err!(seq.dev, "Sequencer: sec2 errors: {:?}\n", mbox0);
+ return Err(EIO);
+ }
+
+ // Write the OS version to the GSP falcon.
+ seq.gsp_falcon
+ .write_os_version(seq.bar, seq.fw.gsp_bootloader.app_version)?;
+
+ // Check if the RISC-V core is active, return error if not
+ if !seq.gsp_falcon.is_riscv_active(seq.bar)? {
+ dev_err!(seq.dev, "Sequencer: RISC-V core is not active\n");
+ return Err(EIO);
+ }
+ Ok(())
+ }
}
}
}
diff --git a/drivers/gpu/nova-core/nvfw.rs b/drivers/gpu/nova-core/nvfw.rs
index 0b44a922fe5d..39e5f3d5b432 100644
--- a/drivers/gpu/nova-core/nvfw.rs
+++ b/drivers/gpu/nova-core/nvfw.rs
@@ -41,7 +41,6 @@ pub(crate) struct LibosParams {
/// addresses of the GSP bootloader and firmware.
pub(crate) use r570_144::GspFwWprMeta;
-#[expect(unused_imports)]
pub(crate) use r570_144::{
rpc_run_cpu_sequencer_v17_00,
// Core GSP structures
--
2.34.1
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