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Message-ID: <877c2edd-851d-4722-8bb4-94fdc3c058a0@ti.com>
Date: Fri, 29 Aug 2025 11:32:48 +0530
From: Beleswar Prasad Padhi <b-padhi@...com>
To: Wadim Egorov <w.egorov@...tec.de>, <nm@...com>, <vigneshr@...com>,
        <kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
        <conor+dt@...nel.org>
CC: <afd@...com>, <u-kumar1@...com>, <hnagalla@...com>, <jm@...com>,
        <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>, Matt McKee <mmckee@...tec.com>,
        Garrett Giordano <ggiordano@...tec.com>,
        Nathan Morrisson
	<nmorrisson@...tec.com>, John Ma <jma@...tec.com>,
        Logan Bristol
	<logan.bristol@...xas.edu>
Subject: Re: [PATCH v2 18/33] arm64: dts: ti: k3-am64-phycore-som: Add missing
 cfg for TI IPC Firmware

Hi Wadim,

On 28/08/25 17:12, Wadim Egorov wrote:
>
>
> On 8/23/25 7:08 PM, Beleswar Padhi wrote:
>> The k3-am64-phycore SoM enables all R5F and M4F remote processors.
>> Reserve the MAIN domain timers that are used by R5F remote
>> processors for ticks to avoid rproc crashes. This config aligns with
>> other AM64 boards and can be refactored out later.
>>
>> Signed-off-by: Beleswar Padhi <b-padhi@...com>
>
> I am not sure you need this patch, because you are deleting everything you add in patch 32.


I am also including the "k3-am64-ti-ipc-firmware.dtsi" in patch [32/33]
which has these timer configurations.

This [18/33] is an intermediate patch. We are putting all AM64* boards
into same configuration first before refactoring everything into a
common file [32/33]. That way if there is a bug someday in the future,
due to added configs, the bisect lands on the [18/33] patch and not on
the refactoring patch[32/33].

Just trying to keep every file same before & after the refactoring patch

> But I tested the series on our hardware, so
>
> Tested-by: Wadim Egorov <w.egorov@...tec.de>


Thanks,
Beleswar

>
>> ---
>> Cc: Wadim Egorov <w.egorov@...tec.de>
>> Cc: Matt McKee <mmckee@...tec.com>
>> Cc: Garrett Giordano <ggiordano@...tec.com>
>> Cc: Nathan Morrisson <nmorrisson@...tec.com>
>> Cc: John Ma <jma@...tec.com>
>> Cc: Logan Bristol <logan.bristol@...xas.edu>
>> Requesting for review/test of this patch.
>>
>> v2: Changelog:
>> 1. Re-ordered patch from [PATCH 28/33] to [PATCH v2 18/33].
>>
>> Link to v1:
>> https://lore.kernel.org/all/20250814223839.3256046-29-b-padhi@ti.com/
>>
>>   .../boot/dts/ti/k3-am64-phycore-som.dtsi      | 24 +++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> index 03c46d74ebb5..1efd547b2ba6 100644
>> --- a/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-am64-phycore-som.dtsi
>> @@ -275,6 +275,30 @@ mbox_m4_0: mbox-m4-0 {
>>       };
>>   };
>>   +/* main_timer8 is used by r5f0-0 */
>> +&main_timer8 {
>> +    status = "reserved";
>> +};
>> +
>> +/* main_timer9 is used by r5f0-1 */
>> +&main_timer9 {
>> +    status = "reserved";
>> +};
>> +
>> +/* main_timer10 is used by r5f1-0 */
>> +&main_timer10 {
>> +    status = "reserved";
>> +};
>> +
>> +/* main_timer11 is used by r5f1-1 */
>> +&main_timer11 {
>> +    status = "reserved";
>> +};
>> +
>> +&main_r5fss0 {
>> +    status = "okay";
>> +};
>> +
>>   &main_i2c0 {
>>       pinctrl-names = "default";
>>       pinctrl-0 = <&main_i2c0_pins_default>;
>

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