linux-kernel - Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support

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Message-ID: <20250829-attentive-watchful-guan-b79ccc@kuoka>
Date: Fri, 29 Aug 2025 09:56:06 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Ravi Patel <ravi.patel@...sung.com>
Cc: jesper.nilsson@...s.com, mturquette@...libre.com, sboyd@...nel.org, 
	robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, s.nawrocki@...sung.com, 
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	tomasz.figa@...il.com, catalin.marinas@....com, will@...nel.org, arnd@...db.de, 
	ksk4725@...sia.com, kenkim@...sia.com, pjsin865@...sia.com, gwk1013@...sia.com, 
	hgkim05@...sia.com, mingyoungbo@...sia.com, smn1196@...sia.com, 
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	hypmean.kim@...sung.com, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, linux-arm-kernel@...s.com, 
	linux-clk@...r.kernel.org, devicetree@...r.kernel.org, linux-gpio@...r.kernel.org, 
	soc@...ts.linux.dev
Subject: Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8
 SoC support

On Mon, Aug 25, 2025 at 05:14:34PM +0530, Ravi Patel wrote:
>  config ARCH_AXIADO
>  	bool "Axiado SoC Family"
>  	select GPIOLIB
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index bdb9e9813e50..bcca63136557 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,4 +1,5 @@
>  # SPDX-License-Identifier: GPL-2.0
> +subdir-y += axis
>  subdir-y += google
>  
>  dtb-$(CONFIG_ARCH_EXYNOS) += \
> diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
> new file mode 100644
> index 000000000000..70bd1dcac85e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
> @@ -0,0 +1,36 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

Does not match rest of licenses.

> +/*
> + * Axis ARTPEC-8 SoC device tree pinctrl constants
> + *
> + * Copyright (c) 2025 Samsung Electronics Co., Ltd.
> + *             https://www.samsung.com
> + * Copyright (c) 2025  Axis Communications AB.
> + *             https://www.axis.com
> + */
> +
> +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
> +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
> +
> +#define ARTPEC_PIN_PULL_NONE		0
> +#define ARTPEC_PIN_PULL_DOWN		1
> +#define ARTPEC_PIN_PULL_UP		3
> +
> +#define ARTPEC_PIN_FUNC_INPUT		0
> +#define ARTPEC_PIN_FUNC_OUTPUT		1
> +#define ARTPEC_PIN_FUNC_2		2
> +#define ARTPEC_PIN_FUNC_3		3
> +#define ARTPEC_PIN_FUNC_4		4
> +#define ARTPEC_PIN_FUNC_5		5
> +#define ARTPEC_PIN_FUNC_6		6
> +#define ARTPEC_PIN_FUNC_EINT		0xf
> +#define ARTPEC_PIN_FUNC_F		ARTPEC_PIN_FUNC_EINT
> +
> +/* Drive strength for ARTPEC */
> +#define ARTPEC_PIN_DRV_SR1		0x8
> +#define ARTPEC_PIN_DRV_SR2		0x9
> +#define ARTPEC_PIN_DRV_SR3		0xa
> +#define ARTPEC_PIN_DRV_SR4		0xb
> +#define ARTPEC_PIN_DRV_SR5		0xc
> +#define ARTPEC_PIN_DRV_SR6		0xd
> +
> +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */
> diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
> new file mode 100644
> index 000000000000..8d239a70f1b4
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)

This is Dual license, so why pincltr header is not?

Best regards,
Krzysztof