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Message-Id: <20250828-clk-round-rate-v2-v1-4-b97ec8ba6cc4@redhat.com>
Date: Thu, 28 Aug 2025 20:38:23 -0400
From: Brian Masney <bmasney@...hat.com>
To: Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Vladimir Zapolskiy <vz@...ia.com>,
Piotr Wojtaszczyk <piotr.wojtaszczyk@...esys.com>,
Chen Wang <unicorn_wang@...look.com>, Inochi Amaoto <inochiama@...il.com>,
Michal Simek <michal.simek@....com>, Bjorn Andersson <andersson@...nel.org>,
Heiko Stuebner <heiko@...ech.de>,
Andrea della Porta <andrea.porta@...e.com>,
Maxime Ripard <mripard@...nel.org>
Cc: linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, sophgo@...ts.linux.dev,
linux-arm-msm@...r.kernel.org, linux-rockchip@...ts.infradead.org,
Brian Masney <bmasney@...hat.com>
Subject: [PATCH 4/8] clk: rp1: convert from round_rate() to
determine_rate()
The round_rate() clk ops is deprecated, so migrate this driver from
round_rate() to determine_rate() using the Coccinelle semantic patch
on the cover letter of this series.
Signed-off-by: Brian Masney <bmasney@...hat.com>
---
drivers/clk/clk-rp1.c | 58 +++++++++++++++++++++++++++++----------------------
1 file changed, 33 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/clk-rp1.c b/drivers/clk/clk-rp1.c
index e8f264d7f34e42f7186dbba31e5ace95d67b9a7d..fd144755b879862612ea5e22e913dbb44a140033 100644
--- a/drivers/clk/clk-rp1.c
+++ b/drivers/clk/clk-rp1.c
@@ -532,13 +532,16 @@ static unsigned long rp1_pll_core_recalc_rate(struct clk_hw *hw,
return calc_rate;
}
-static long rp1_pll_core_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int rp1_pll_core_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
u32 fbdiv_int, fbdiv_frac;
- return get_pll_core_divider(hw, rate, *parent_rate,
- &fbdiv_int, &fbdiv_frac);
+ req->rate = get_pll_core_divider(hw, req->rate, req->best_parent_rate,
+ &fbdiv_int,
+ &fbdiv_frac);
+
+ return 0;
}
static void get_pll_prim_dividers(unsigned long rate, unsigned long parent_rate,
@@ -616,18 +619,20 @@ static unsigned long rp1_pll_recalc_rate(struct clk_hw *hw,
return DIV_ROUND_CLOSEST(parent_rate, prim_div1 * prim_div2);
}
-static long rp1_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int rp1_pll_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
struct clk_hw *clk_audio_hw = &clk_audio->hw;
u32 div1, div2;
- if (hw == clk_audio_hw && clk_audio->cached_rate == rate)
- *parent_rate = clk_audio_core->cached_rate;
+ if (hw == clk_audio_hw && clk_audio->cached_rate == req->rate)
+ req->best_parent_rate = clk_audio_core->cached_rate;
+
+ get_pll_prim_dividers(req->rate, req->best_parent_rate, &div1, &div2);
- get_pll_prim_dividers(rate, *parent_rate, &div1, &div2);
+ req->rate = DIV_ROUND_CLOSEST(req->best_parent_rate, div1 * div2);
- return DIV_ROUND_CLOSEST(*parent_rate, div1 * div2);
+ return 0;
}
static int rp1_pll_ph_is_on(struct clk_hw *hw)
@@ -677,13 +682,15 @@ static unsigned long rp1_pll_ph_recalc_rate(struct clk_hw *hw,
return parent_rate / data->fixed_divider;
}
-static long rp1_pll_ph_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int rp1_pll_ph_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
struct rp1_clk_desc *pll_ph = container_of(hw, struct rp1_clk_desc, hw);
const struct rp1_pll_ph_data *data = pll_ph->data;
- return *parent_rate / data->fixed_divider;
+ req->rate = req->best_parent_rate / data->fixed_divider;
+
+ return 0;
}
static int rp1_pll_divider_is_on(struct clk_hw *hw)
@@ -760,11 +767,12 @@ static unsigned long rp1_pll_divider_recalc_rate(struct clk_hw *hw,
return clk_divider_ops.recalc_rate(hw, parent_rate);
}
-static long rp1_pll_divider_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static int rp1_pll_divider_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- return clk_divider_ops.round_rate(hw, rate, parent_rate);
+ req->rate = clk_divider_ops.determine_rate(hw, req);
+
+ return 0;
}
static int rp1_clock_is_on(struct clk_hw *hw)
@@ -1166,10 +1174,10 @@ static unsigned long rp1_varsrc_recalc_rate(struct clk_hw *hw,
return clock->cached_rate;
}
-static long rp1_varsrc_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static int rp1_varsrc_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
{
- return rate;
+ return 0;
}
static const struct clk_ops rp1_pll_core_ops = {
@@ -1178,13 +1186,13 @@ static const struct clk_ops rp1_pll_core_ops = {
.unprepare = rp1_pll_core_off,
.set_rate = rp1_pll_core_set_rate,
.recalc_rate = rp1_pll_core_recalc_rate,
- .round_rate = rp1_pll_core_round_rate,
+ .determine_rate = rp1_pll_core_determine_rate,
};
static const struct clk_ops rp1_pll_ops = {
.set_rate = rp1_pll_set_rate,
.recalc_rate = rp1_pll_recalc_rate,
- .round_rate = rp1_pll_round_rate,
+ .determine_rate = rp1_pll_determine_rate,
};
static const struct clk_ops rp1_pll_ph_ops = {
@@ -1192,7 +1200,7 @@ static const struct clk_ops rp1_pll_ph_ops = {
.prepare = rp1_pll_ph_on,
.unprepare = rp1_pll_ph_off,
.recalc_rate = rp1_pll_ph_recalc_rate,
- .round_rate = rp1_pll_ph_round_rate,
+ .determine_rate = rp1_pll_ph_determine_rate,
};
static const struct clk_ops rp1_pll_divider_ops = {
@@ -1201,7 +1209,7 @@ static const struct clk_ops rp1_pll_divider_ops = {
.unprepare = rp1_pll_divider_off,
.set_rate = rp1_pll_divider_set_rate,
.recalc_rate = rp1_pll_divider_recalc_rate,
- .round_rate = rp1_pll_divider_round_rate,
+ .determine_rate = rp1_pll_divider_determine_rate,
};
static const struct clk_ops rp1_clk_ops = {
@@ -1219,7 +1227,7 @@ static const struct clk_ops rp1_clk_ops = {
static const struct clk_ops rp1_varsrc_ops = {
.set_rate = rp1_varsrc_set_rate,
.recalc_rate = rp1_varsrc_recalc_rate,
- .round_rate = rp1_varsrc_round_rate,
+ .determine_rate = rp1_varsrc_determine_rate,
};
static struct clk_hw *rp1_register_pll(struct rp1_clockman *clockman,
--
2.50.1
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