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Message-ID: <CAHp75Vf6xa_ei1WbhGaQ+xKUEp_6JKcXFYJZpQvYd8YN-33S_g@mail.gmail.com>
Date: Sat, 30 Aug 2025 10:38:53 +0300
From: Andy Shevchenko <andy.shevchenko@...il.com>
To: Marcelo Schmitt <marcelo.schmitt@...log.com>
Cc: linux-iio@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-doc@...r.kernel.org, devicetree@...r.kernel.org,
linux-spi@...r.kernel.org, jic23@...nel.org, Michael.Hennerich@...log.com,
nuno.sa@...log.com, eblanc@...libre.com, dlechner@...libre.com,
andy@...nel.org, corbet@....net, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, broonie@...nel.org, Jonathan.Cameron@...wei.com,
andriy.shevchenko@...ux.intel.com, ahaslam@...libre.com,
sergiu.cuciurean@...log.com, marcelo.schmitt1@...il.com
Subject: Re: [PATCH 09/15] iio: adc: ad4030: Support multiple data lanes per channel
On Sat, Aug 30, 2025 at 3:43 AM Marcelo Schmitt
<marcelo.schmitt@...log.com> wrote:
>
> AD4030 and similar chips can output ADC sample data through 1, 2, or 4
> lines per channel. The number of SPI lines the device uses to output data
> is specified in firmware. Parse SPI read bus width setting from firmware
> and configure the device to use that amount of lines to output data.
...
> - offload_bpw = data_width;
> + offload_bpw = data_width / (1 << st->lane_mode);
This is interesting. What's the difference you see to the use of the
right shift?
Also note, in case of lane_mode == 31 (yeah, I understand that here
it's not the case) this is UB in accordance with C standard.
--
With Best Regards,
Andy Shevchenko
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