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Message-ID: <96bced8e-7e47-4db9-9674-be1f3138d608@kernel.org>
Date: Sat, 30 Aug 2025 11:16:37 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Denzeel Oliva <wachiturroxd150@...il.com>,
Sylwester Nawrocki <s.nawrocki@...sung.com>,
Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
Michael Turquette <mturquette@...libre.com>, Stephen Boyd
<sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Conor Dooley <conor+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v4 4/4] clk: samsung: exynos990: Fix PLL mux regs, add
DPU/CMUREF
On 25/08/2025 07:51, Denzeel Oliva wrote:
> Switch PLL muxes to PLL_CON0 to correct parent selection and
> clock rates. Add DPU_BUS and CMUREF mux/div and their register
> hooks and parents.
>
> Signed-off-by: Denzeel Oliva <wachiturroxd150@...il.com>
> ---
> drivers/clk/samsung/clk-exynos990.c | 97 ++++++++++++++++++++++++-------------
> 1 file changed, 63 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-exynos990.c
> index 9fcdad7cc..d1135708c 100644
> --- a/drivers/clk/samsung/clk-exynos990.c
> +++ b/drivers/clk/samsung/clk-exynos990.c
> @@ -45,6 +45,7 @@
> #define PLL_CON3_PLL_SHARED3 0x024c
> #define PLL_CON0_PLL_SHARED4 0x0280
> #define PLL_CON3_PLL_SHARED4 0x028c
> +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000
> #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004
> #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008
> #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c
> @@ -103,6 +104,8 @@
> #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0
> #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4
> #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8
> +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0
> +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4
> #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800
> #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804
> #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808
> @@ -162,6 +165,7 @@
> #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0
> #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8
> #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec
> +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0
> #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4
> #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8
> #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc
> @@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst = {
> PLL_LOCKTIME_PLL_SHARED2,
> PLL_LOCKTIME_PLL_SHARED3,
> PLL_LOCKTIME_PLL_SHARED4,
> + PLL_CON0_PLL_G3D,
> PLL_CON3_PLL_G3D,
> + PLL_CON0_PLL_MMC,
> PLL_CON3_PLL_MMC,
> + PLL_CON0_PLL_SHARED0,
> PLL_CON3_PLL_SHARED0,
> + PLL_CON0_PLL_SHARED1,
> PLL_CON3_PLL_SHARED1,
> + PLL_CON0_PLL_SHARED2,
> PLL_CON3_PLL_SHARED2,
> + PLL_CON0_PLL_SHARED3,
> PLL_CON3_PLL_SHARED3,
> + PLL_CON0_PLL_SHARED4,
> PLL_CON3_PLL_SHARED4,
> + CLK_CON_MUX_CLKCMU_DPU_BUS,
> CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
> CLK_CON_MUX_MUX_CLKCMU_AUD_CPU,
> CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
> @@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_MUX_MUX_CLKCMU_SSP_BUS,
> CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
> CLK_CON_MUX_MUX_CLKCMU_VRA_BUS,
> + CLK_CON_MUX_MUX_CLK_CMU_CMUREF,
> + CLK_CON_MUX_MUX_CMU_CMUREF,
> CLK_CON_DIV_CLKCMU_APM_BUS,
> CLK_CON_DIV_CLKCMU_AUD_CPU,
> CLK_CON_DIV_CLKCMU_BUS0_BUS,
> @@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_DIV_CLKCMU_VRA_BUS,
> CLK_CON_DIV_DIV_CLKCMU_DPU,
> CLK_CON_DIV_DIV_CLKCMU_DPU_ALT,
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
> CLK_CON_DIV_PLL_SHARED0_DIV2,
> CLK_CON_DIV_PLL_SHARED0_DIV3,
> CLK_CON_DIV_PLL_SHARED0_DIV4,
> @@ -458,6 +473,8 @@ PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
> PNAME(mout_pll_shared4_p) = { "oscclk", "fout_shared4_pll" };
> PNAME(mout_pll_mmc_p) = { "oscclk", "fout_mmc_pll" };
> PNAME(mout_pll_g3d_p) = { "oscclk", "fout_g3d_pll" };
> +PNAME(mout_cmu_dpu_bus_p) = { "dout_cmu_dpu",
> + "dout_cmu_dpu_alt" };
> PNAME(mout_cmu_apm_bus_p) = { "dout_cmu_shared0_div2",
> "dout_cmu_shared2_div2" };
> PNAME(mout_cmu_aud_cpu_p) = { "dout_cmu_shared0_div2",
> @@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared4_pll",
> "dout_cmu_shared0_div2",
> "fout_shared2_pll",
> "dout_cmu_shared0_div4" };
> -PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
> +PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared4_pll",
I don't understand this change.
> "dout_cmu_shared0_div2",
> "fout_shared2_pll",
> "dout_cmu_shared0_div4" };
> @@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div3",
> "dout_cmu_shared4_div3",
> "dout_cmu_shared2_div2",
> "fout_mmc_pll", "oscclk", "oscclk" };
> -PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
> +PNAME(mout_cmu_hsi1_mmc_card_p) = { "oscclk", "fout_shared2_pll",
Neither this, looks like you changed nothing here.
> "fout_mmc_pll",
> "dout_cmu_shared0_div4" };
> PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "fout_shared2_pll" };
> @@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
> "dout_cmu_shared4_div2",
> "dout_cmu_shared0_div4",
> "dout_cmu_shared4_div3" };
> +PNAME(mout_cmu_cmuref_p) = { "oscclk",
> + "dout_cmu_clk_cmuref" };
> +PNAME(mout_cmu_clk_cmuref_p) = { "dout_cmu_shared0_div4",
> + "dout_cmu_shared1_div4",
> + "dout_cmu_shared2_div2",
> + "oscclk" };
>
> /*
> * Register name to clock name mangling strategy used in this file
> @@ -689,19 +712,21 @@ PNAME(mout_cmu_vra_bus_p) = { "dout_cmu_shared0_div3",
>
> static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
> - PLL_CON3_PLL_SHARED0, 4, 1),
> + PLL_CON0_PLL_SHARED0, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
> - PLL_CON3_PLL_SHARED1, 4, 1),
> + PLL_CON0_PLL_SHARED1, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
> - PLL_CON3_PLL_SHARED2, 4, 1),
> + PLL_CON0_PLL_SHARED2, 4, 1),
> MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
> - PLL_CON3_PLL_SHARED3, 4, 1),
> + PLL_CON0_PLL_SHARED3, 4, 1),
This looks like fix, so shuold be sent separately with Fixes tag.
> MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p,
> PLL_CON0_PLL_SHARED4, 4, 1),
> MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p,
> PLL_CON0_PLL_MMC, 4, 1),
> MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p,
> PLL_CON0_PLL_G3D, 4, 1),
> + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus",
> + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1),
> MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus",
> mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
> MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu",
> @@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
> MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus",
> mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2),
> + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref",
> + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
> + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref",
> + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2),
> };
>
> static const struct samsung_div_clock top_div_clks[] __initconst = {
> - /* SHARED0 region*/
> - DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0",
> - CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0",
> - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0_div2",
> - CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
And this is not really explained in the commit msg.
> -
> - /* SHARED1 region*/
> - DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1",
> - CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1",
> - CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1_div2",
> - CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
> -
> - /* SHARED2 region */
> - DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2",
> - CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
> -
> - /* SHARED4 region*/
> - DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1),
> - DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2),
> - DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4",
> - CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1),
> -
> DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus",
> CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2),
> DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu",
> @@ -974,6 +975,34 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4),
> DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu",
> CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3),
> + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus",
> + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4),
> + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref",
> + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
Best regards,
Krzysztof
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