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Message-ID: <5d03a10f-5281-49a7-b578-b45d7b69209c@baylibre.com>
Date: Sat, 30 Aug 2025 12:27:42 -0500
From: David Lechner <dlechner@...libre.com>
To: Marcelo Schmitt <marcelo.schmitt@...log.com>, linux-iio@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-doc@...r.kernel.org,
devicetree@...r.kernel.org, linux-spi@...r.kernel.org
Cc: jic23@...nel.org, Michael.Hennerich@...log.com, nuno.sa@...log.com,
eblanc@...libre.com, andy@...nel.org, corbet@....net, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, broonie@...nel.org,
Jonathan.Cameron@...wei.com, andriy.shevchenko@...ux.intel.com,
ahaslam@...libre.com, sergiu.cuciurean@...log.com, marcelo.schmitt1@...il.com
Subject: Re: [PATCH 12/15] dt-bindings: iio: adc: adi,ad4030: Add
adi,dual-data-rate
On 8/29/25 7:44 PM, Marcelo Schmitt wrote:
> On echo and host clock modes, AD4030 and similar devices can do two data
> bit transitions per clock cycle per active lane. Document how to specify
> dual data rate (DDR) feature for AD4030 series devices in device tree.
>
I don't think this needs to be in the devicetree. Dual data rate doesn't
depend on wiring, it only depends on if the SPI controller supports it
or not. The core SPI code in Linux already has dtr_caps for SPI controllers
to indicate that they have DDR support. So an ADC driver can just check
this flag to see if the controller supports it. No devicetree flags required.
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