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Message-ID: <fv4jz6unxpncqazgptet4ie67vdrqqnq3owpjuh7huqvepoozd@yelivqgci2om>
Date: Sun, 31 Aug 2025 13:00:23 +0300
From: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
To: Barnabás Czémán <barnabas.czeman@...nlining.org>
Cc: Bjorn Andersson <andersson@...nel.org>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Stephan Gerhold <stephan@...hold.net>,
Otto Pflüger <otto.pflueger@...cue.de>,
Linus Walleij <linus.walleij@...aro.org>, Lee Jones <lee@...nel.org>,
Joerg Roedel <joro@...tes.org>, Will Deacon <will@...nel.org>,
Robin Murphy <robin.murphy@....com>,
Konrad Dybcio <konradybcio@...nel.org>, Sean Paul <sean@...rly.run>,
Abhinav Kumar <quic_abhinavk@...cinc.com>,
Marijn Suijten <marijn.suijten@...ainline.org>,
David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>,
Maarten Lankhorst <maarten.lankhorst@...ux.intel.com>,
Maxime Ripard <mripard@...nel.org>,
Thomas Zimmermann <tzimmermann@...e.de>,
Dmitry Baryshkov <lumag@...nel.org>,
Adam Skladowski <a_skl39@...tonmail.com>,
Sireesh Kodali <sireeshkodali@...tonmail.com>,
Rob Clark <robin.clark@....qualcomm.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
Jessica Zhang <jessica.zhang@....qualcomm.com>,
Srinivas Kandagatla <srini@...nel.org>, linux-arm-msm@...r.kernel.org,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-gpio@...r.kernel.org,
iommu@...ts.linux.dev, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, phone-devel@...r.kernel.org,
~postmarketos/upstreaming@...ts.sr.ht, linux@...nlining.org,
Dang Huynh <danct12@...eup.net>
Subject: Re: [PATCH v7 4/6] arm64: dts: qcom: Add initial support for MSM8937
On Sun, Aug 31, 2025 at 12:38:16AM +0200, Barnabás Czémán wrote:
> From: Dang Huynh <danct12@...eup.net>
>
> Add initial support for MSM8937 SoC.
>
> Signed-off-by: Dang Huynh <danct12@...eup.net>
> Co-developed-by: Barnabás Czémán <barnabas.czeman@...nlining.org>
> Signed-off-by: Barnabás Czémán <barnabas.czeman@...nlining.org>
> ---
> arch/arm64/boot/dts/qcom/msm8937.dtsi | 2134 +++++++++++++++++++++++++++++++++
> 1 file changed, 2134 insertions(+)
> + };
> +
> +
> + firmware {
> + scm: scm {
> + compatible = "qcom,scm-msm8916", "qcom,scm";
"qcom,scm-msm8937", "qcom,scm"
> + clocks = <&gcc GCC_CRYPTO_CLK>,
> + <&gcc GCC_CRYPTO_AXI_CLK>,
> + <&gcc GCC_CRYPTO_AHB_CLK>;
> + clock-names = "core",
> + "bus",
> + "iface";
> + #reset-cells = <1>;
> +
> + qcom,dload-mode = <&tcsr 0x6100>;
> + };
> + };
> +
> + memory@...00000 {
> + /* We expect the bootloader to fill in the reg */
> + reg = <0 0x80000000 0 0>;
> + device_type = "memory";
> + };
> +
> + reserved-memory {
> + ranges;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + qseecom_mem: reserved@...00000 {
> + reg = <0x0 0x85b00000 0x0 0x800000>;
> + no-map;
> + };
> +
> + smem@...00000 {
> + compatible = "qcom,smem";
> + reg = <0x0 0x86300000 0x0 0x100000>;
> + no-map;
> +
> + hwlocks = <&tcsr_mutex 3>;
> + qcom,rpm-msg-ram = <&rpm_msg_ram>;
> + };
> +
> + reserved@...00000 {
> + reg = <0x0 0x86400000 0x0 0x400000>;
> + no-map;
> + };
> +
> + rmtfs@...00000 {
> + compatible = "qcom,rmtfs-mem";
> + reg = <0x0 0x92100000 0x0 0x180000>;
> + no-map;
> +
> + qcom,client-id = <1>;
> + };
> +
> + adsp_mem: adsp {
> + size = <0x0 0x1100000>;
> + alignment = <0x0 0x100000>;
> + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> + no-map;
> + status = "disabled";
> + };
> +
> + mba_mem: mba {
> + size = <0x0 0x100000>;
> + alignment = <0x0 0x100000>;
> + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> + no-map;
> + status = "disabled";
> + };
> +
> + wcnss_mem: wcnss {
> + size = <0x0 0x700000>;
> + alignment = <0x0 0x100000>;
> + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> + no-map;
> + status = "disabled";
> + };
> +
> + venus_mem: venus {
> + size = <0x0 0x400000>;
> + alignment = <0x0 0x100000>;
> + alloc-ranges = <0x0 0x86800000 0x0 0x8000000>;
> + no-map;
> + status = "disabled";
> + };
> + };
> +
> + cpu_opp_table_c0: opp-table-c0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-768000000 {
> + opp-hz = /bits/ 64 <768000000>;
> + };
> +
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + };
> +
> + opp-998400000 {
> + opp-hz = /bits/ 64 <998400000>;
> + };
> +
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + };
> + };
> +
> + cpu_opp_table_c1: opp-table-c1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp-960000000 {
> + opp-hz = /bits/ 64 <960000000>;
> + };
> +
> + opp-1094400000 {
> + opp-hz = /bits/ 64 <1094400000>;
> + };
> +
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + };
> +
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + };
> +
> + opp-1344000000 {
> + opp-hz = /bits/ 64 <1344000000>;
> + };
> +
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + };
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + rpm: remoteproc {
> + compatible = "qcom,msm8937-rpm-proc", "qcom,rpm-proc";
> +
> + smd-edge {
> + interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
> + qcom,ipc = <&apcs1 8 0>;
> + qcom,smd-edge = <15>;
> +
> + rpm_requests: rpm-requests {
> + compatible = "qcom,rpm-msm8937", "qcom,smd-rpm";
> + qcom,smd-channels = "rpm_requests";
> +
> + rpmcc: clock-controller {
> + compatible = "qcom,rpmcc-msm8937", "qcom,rpmcc";
> + #clock-cells = <1>;
> + clocks = <&xo_board>;
> + clock-names = "xo";
> + };
> +
> + rpmpd: power-controller {
> + compatible = "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd";
> + #power-domain-cells = <1>;
> + operating-points-v2 = <&rpmpd_opp_table>;
> +
> + rpmpd_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + rpmpd_opp_ret: opp1 {
> + opp-level = <RPM_SMD_LEVEL_RETENTION>;
> + };
> +
> + rpmpd_opp_ret_plus: opp2 {
> + opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
> + };
> +
> + rpmpd_opp_min_svs: opp3 {
> + opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
> + };
> +
> + rpmpd_opp_low_svs: opp4 {
> + opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
> + };
> +
> + rpmpd_opp_svs: opp5 {
> + opp-level = <RPM_SMD_LEVEL_SVS>;
> + };
> +
> + rpmpd_opp_svs_plus: opp6 {
> + opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
> + };
> +
> + rpmpd_opp_nom: opp7 {
> + opp-level = <RPM_SMD_LEVEL_NOM>;
> + };
> +
> + rpmpd_opp_nom_plus: opp8 {
> + opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
> + };
> +
> + rpmpd_opp_turbo: opp9 {
> + opp-level = <RPM_SMD_LEVEL_TURBO>;
> + };
> + };
> + };
> + };
> + };
> + };
> +
> + smp2p-adsp {
> + compatible = "qcom,smp2p";
> + qcom,smem = <443>, <429>;
> +
> + interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apcs1 10>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <2>;
> +
> + adsp_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> +
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + adsp_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-modem {
> + compatible = "qcom,smp2p";
> + qcom,smem = <435>, <428>;
> +
> + interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apcs1 14>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <1>;
> +
> + modem_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> +
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + modem_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smp2p-wcnss {
> + compatible = "qcom,smp2p";
> + qcom,smem = <451>, <431>;
> +
> + interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>;
> +
> + mboxes = <&apcs1 18>;
> +
> + qcom,local-pid = <0>;
> + qcom,remote-pid = <4>;
> +
> + wcnss_smp2p_out: master-kernel {
> + qcom,entry-name = "master-kernel";
> +
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + wcnss_smp2p_in: slave-kernel {
> + qcom,entry-name = "slave-kernel";
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + smsm {
> + compatible = "qcom,smsm";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + mboxes = <0>, <&apcs1 13>, <0>, <&apcs1 19>;
> +
> + apps_smsm: apps@0 {
> + reg = <0>;
> +
> + #qcom,smem-state-cells = <1>;
> + };
> +
> + hexagon_smsm: hexagon@1 {
> + reg = <1>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + wcnss_smsm: wcnss@6 {
> + reg = <6>;
> + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +
> + soc: soc@0 {
> + compatible = "simple-bus";
> + ranges = <0 0 0 0xffffffff>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + qfprom: qfprom@...00 {
> + compatible = "qcom,msm8937-qfprom", "qcom,qfprom";
> + reg = <0x000a4000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + tsens_base1: base1@1d8 {
> + reg = <0x1d8 0x1>;
> + bits = <0 8>;
> + };
> +
> + tsens_s5_p1: s5-p1@1d9 {
> + reg = <0x1d9 0x1>;
> + bits = <0 6>;
> + };
> +
> + tsens_s5_p2: s5-p2@1d9 {
> + reg = <0x1d9 0x2>;
> + bits = <6 6>;
> + };
> +
> + tsens_s6_p1: s6-p1@1da {
> + reg = <0x1da 0x2>;
> + bits = <4 6>;
> + };
> +
> + tsens_s6_p2: s6-p2@1db {
> + reg = <0x1db 0x1>;
> + bits = <2 6>;
> + };
> +
> + tsens_s7_p1: s7-p1@1dc {
> + reg = <0x1dc 0x1>;
> + bits = <0 6>;
> + };
> +
> + tsens_s7_p2: s7-p2@1dc {
> + reg = <0x1dc 0x2>;
> + bits = <6 6>;
> + };
> +
> + tsens_s8_p1: s8-p1@1dd {
> + reg = <0x1dd 0x2>;
> + bits = <4 6>;
> + };
> +
> + tsens_s8_p2: s8-p2@1de {
> + reg = <0x1de 0x1>;
> + bits = <2 6>;
> + };
> +
> + tsens_base2: base2@1df {
> + reg = <0x1df 0x1>;
> + bits = <0 8>;
> + };
> +
> + tsens_mode: mode@210 {
> + reg = <0x210 0x1>;
> + bits = <0 3>;
> + };
> +
> + tsens_s0_p1: s0-p1@210 {
> + reg = <0x210 0x2>;
> + bits = <3 6>;
> + };
> +
> + tsens_s0_p2: s0-p2@211 {
> + reg = <0x211 0x1>;
> + bits = <1 6>;
> + };
> +
> + tsens_s1_p1: s1-p1@211 {
> + reg = <0x211 0x2>;
> + bits = <7 6>;
> + };
> +
> + tsens_s1_p2: s1-p2@212 {
> + reg = <0x212 0x2>;
> + bits = <5 6>;
> + };
> +
> + tsens_s2_p1: s2-p1@213 {
> + reg = <0x213 0x2>;
> + bits = <3 6>;
> + };
> +
> + tsens_s2_p2: s2-p2@214 {
> + reg = <0x214 0x1>;
> + bits = <1 6>;
> + };
> +
> + tsens_s3_p1: s3-p1@214 {
> + reg = <0x214 0x2>;
> + bits = <7 6>;
> + };
> +
> + tsens_s3_p2: s3-p2@215 {
> + reg = <0x215 0x2>;
> + bits = <5 6>;
> + };
> +
> + tsens_s4_p1: s4-p1@216 {
> + reg = <0x216 0x2>;
> + bits = <3 6>;
> + };
> +
> + tsens_s4_p2: s4-p2@217 {
> + reg = <0x217 0x1>;
> + bits = <1 6>;
> + };
> +
> + tsens_s9_p1: s9-p1@230 {
> + reg = <0x230 0x1>;
> + bits = <0 6>;
> + };
> +
> + tsens_s9_p2: s9-p2@230 {
> + reg = <0x230 0x2>;
> + bits = <6 6>;
> + };
> +
> + tsens_s10_p1: s10-p1@231 {
> + reg = <0x231 0x2>;
> + bits = <4 6>;
> + };
> +
> + tsens_s10_p2: s10-p2@232 {
> + reg = <0x232 0x1>;
> + bits = <2 6>;
> + };
> +
> + gpu_speed_bin: gpu-speed-bin@...b {
> + reg = <0x601b 0x1>;
> + bits = <7 1>;
> + };
> + };
> +
> + usb_hs_phy: phy@...00 {
> + compatible = "qcom,usb-hs-28nm-femtophy";
> + reg = <0x0006c000 0x200>;
> + #phy-cells = <0>;
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
> + <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
> + clock-names = "ref",
> + "ahb",
> + "sleep";
> + resets = <&gcc GCC_QUSB2_PHY_BCR>,
> + <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
> + reset-names = "phy",
> + "por";
> + status = "disabled";
> + };
> +
> + rng@...00 {
> + compatible = "qcom,prng";
> + reg = <0x000e3000 0x1000>;
> + clocks = <&gcc GCC_PRNG_AHB_CLK>;
> + clock-names = "core";
> + };
> +
> + tsens: thermal-sensor@...000 {
> + compatible = "qcom,msm8937-tsens", "qcom,tsens-v1";
> + reg = <0x004a9000 0x1000>,
> + <0x004a8000 0x1000>;
> + interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "uplow";
> + nvmem-cells = <&tsens_mode>,
> + <&tsens_base1>, <&tsens_base2>,
> + <&tsens_s0_p1>, <&tsens_s0_p2>,
> + <&tsens_s1_p1>, <&tsens_s1_p2>,
> + <&tsens_s2_p1>, <&tsens_s2_p2>,
> + <&tsens_s3_p1>, <&tsens_s3_p2>,
> + <&tsens_s4_p1>, <&tsens_s4_p2>,
> + <&tsens_s5_p1>, <&tsens_s5_p2>,
> + <&tsens_s6_p1>, <&tsens_s6_p2>,
> + <&tsens_s7_p1>, <&tsens_s7_p2>,
> + <&tsens_s8_p1>, <&tsens_s8_p2>,
> + <&tsens_s9_p1>, <&tsens_s9_p2>,
> + <&tsens_s10_p1>, <&tsens_s10_p2>;
> + nvmem-cell-names = "mode",
> + "base1", "base2",
> + "s0_p1", "s0_p2",
> + "s1_p1", "s1_p2",
> + "s2_p1", "s2_p2",
> + "s3_p1", "s3_p2",
> + "s4_p1", "s4_p2",
> + "s5_p1", "s5_p2",
> + "s6_p1", "s6_p2",
> + "s7_p1", "s7_p2",
> + "s8_p1", "s8_p2",
> + "s9_p1", "s9_p2",
> + "s10_p1", "s10_p2";
> + #qcom,sensors = <11>;
> + #thermal-sensor-cells = <1>;
> + };
> +
> + rpm_msg_ram: sram@...00 {
This node is wrongly placed.
> + compatible = "qcom,rpm-msg-ram";
> + reg = <0x00060000 0x8000>;
> + };
> +
> + restart@...000 {
> + compatible = "qcom,pshold";
> + reg = <0x004ab000 0x4>;
> + };
> +
--
With best wishes
Dmitry
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