linux-kernel - Re: [PATCH v5 1/5] clk: samsung: exynos990: Use PLL

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Message-ID: <f4f98fd8-2282-491a-81a5-fdbcd91b4035@kernel.org>
Date: Sun, 31 Aug 2025 12:54:41 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Denzeel Oliva <wachiturroxd150@...il.com>,
 Sylwester Nawrocki <s.nawrocki@...sung.com>,
 Chanwoo Choi <cw00.choi@...sung.com>, Alim Akhtar <alim.akhtar@...sung.com>,
 Michael Turquette <mturquette@...libre.com>, Stephen Boyd
 <sboyd@...nel.org>, Rob Herring <robh@...nel.org>,
 Conor Dooley <conor+dt@...nel.org>
Cc: linux-samsung-soc@...r.kernel.org, linux-clk@...r.kernel.org,
 linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
 devicetree@...r.kernel.org
Subject: Re: [PATCH v5 1/5] clk: samsung: exynos990: Use PLL_CON0 for PLL
 parent muxes

On 30/08/2025 18:28, Denzeel Oliva wrote:
> Parent select bits for shared PLLs are in PLL_CON0, not PLL_CON3.
> Using the wrong register leads to incorrect parent selection and rates.
> 
> Fixes: bdd03ebf721f ("clk: samsung: Introduce Exynos990 clock controller driver")
> Signed-off-by: Denzeel Oliva <wachiturroxd150@...il.com>
I don't remember if I asked, but please add CC-stable in the future.

I added when applying.

Best regards,
Krzysztof