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Message-ID: <000001dc1af1$4026d700$c0748500$@samsung.com>
Date: Mon, 1 Sep 2025 09:03:52 +0530
From: "Ravi Patel" <ravi.patel@...sung.com>
To: "'Krzysztof Kozlowski'" <krzk@...nel.org>
Cc: <jesper.nilsson@...s.com>, <mturquette@...libre.com>,
	<sboyd@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
	<conor+dt@...nel.org>, <s.nawrocki@...sung.com>, <cw00.choi@...sung.com>,
	<alim.akhtar@...sung.com>, <linus.walleij@...aro.org>,
	<tomasz.figa@...il.com>, <catalin.marinas@....com>, <will@...nel.org>,
	<arnd@...db.de>, <ksk4725@...sia.com>, <kenkim@...sia.com>,
	<pjsin865@...sia.com>, <gwk1013@...sia.com>, <hgkim05@...sia.com>,
	<mingyoungbo@...sia.com>, <smn1196@...sia.com>, <shradha.t@...sung.com>,
	<inbaraj.e@...sung.com>, <swathi.ks@...sung.com>,
	<hrishikesh.d@...sung.com>, <dj76.yang@...sung.com>,
	<hypmean.kim@...sung.com>, <linux-kernel@...r.kernel.org>,
	<linux-arm-kernel@...ts.infradead.org>, <linux-samsung-soc@...r.kernel.org>,
	<linux-arm-kernel@...s.com>, <linux-clk@...r.kernel.org>,
	<devicetree@...r.kernel.org>, <linux-gpio@...r.kernel.org>,
	<soc@...ts.linux.dev>
Subject: RE: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8
 SoC support



> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@...nel.org>
> Sent: 29 August 2025 13:26
...
> Subject: Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
> 
> On Mon, Aug 25, 2025 at 05:14:34PM +0530, Ravi Patel wrote:
> >  config ARCH_AXIADO
> >  	bool "Axiado SoC Family"
> >  	select GPIOLIB
> > diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> > index bdb9e9813e50..bcca63136557 100644
> > --- a/arch/arm64/boot/dts/exynos/Makefile
> > +++ b/arch/arm64/boot/dts/exynos/Makefile
> > @@ -1,4 +1,5 @@
> >  # SPDX-License-Identifier: GPL-2.0
> > +subdir-y += axis
> >  subdir-y += google
> >
> >  dtb-$(CONFIG_ARCH_EXYNOS) += \
> > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
> > new file mode 100644
> > index 000000000000..70bd1dcac85e
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h
> > @@ -0,0 +1,36 @@
> > +/* SPDX-License-Identifier: GPL-2.0 */
> 
> Does not match rest of licenses.
> 
> > +/*
> > + * Axis ARTPEC-8 SoC device tree pinctrl constants
> > + *
> > + * Copyright (c) 2025 Samsung Electronics Co., Ltd.
> > + *             https://www.samsung.com
> > + * Copyright (c) 2025  Axis Communications AB.
> > + *             https://www.axis.com
> > + */
> > +
> > +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
> > +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__
> > +
> > +#define ARTPEC_PIN_PULL_NONE		0
...
> > +#define ARTPEC_PIN_DRV_SR6		0xd
> > +
> > +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */
> > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
> > new file mode 100644
> > index 000000000000..8d239a70f1b4
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi
> > @@ -0,0 +1,120 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> 
> This is Dual license, so why pincltr header is not?

Thanks for the review.
I will update the Dual license in pinctrl header in the next version.

Thanks,
Ravi

> 
> Best regards,
> Krzysztof



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