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Message-ID: <CAAhV-H5GixGbrAaJS+hch-LAFt+noCJXHhQD0f7_7BjNfiOncQ@mail.gmail.com>
Date: Mon, 1 Sep 2025 22:24:49 +0800
From: Huacai Chen <chenhuacai@...nel.org>
To: Yao Zi <ziyao@...root.org>
Cc: Yinbo Zhu <zhuyinbo@...ngson.cn>, Linus Walleij <linus.walleij@...aro.org>,
Bartosz Golaszewski <brgl@...ev.pl>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>,
WANG Xuerui <kernel@...0n.name>, Philipp Zabel <p.zabel@...gutronix.de>, linux-gpio@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
loongarch@...ts.linux.dev, Mingcong Bai <jeffbai@...c.io>,
Kexy Biscuit <kexybiscuit@...c.io>
Subject: Re: [PATCH v2 2/3] gpio: loongson-64bit: Add support for Loongson
2K0300 SoC
Hi, Yao,
On Mon, Sep 1, 2025 at 9:38 PM Yao Zi <ziyao@...root.org> wrote:
>
> This controller's input and output logic is similar to previous
> generations of SoCs. Additionally, it's capable of interrupt masking,
> and could be configured to detect levels and edges, and is supplied with
> a distinct reset signal.
>
> The interrupt functionality is implemented through an irqchip, whose
> operations are written with previous generation SoCs in mind and could
> be reused. Since all Loongson SoCs with similar interrupt capability
> (2K1500, 2K2000) support byte-control mode, these operations are for
> byte-control mode only for simplicity.
Modify the name style the same as in Patch-1.
>
> Signed-off-by: Yao Zi <ziyao@...root.org>
> ---
> drivers/gpio/Kconfig | 1 +
> drivers/gpio/gpio-loongson-64bit.c | 191 +++++++++++++++++++++++++++--
> 2 files changed, 185 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index a437fe652dbc..c55173643eb4 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -437,6 +437,7 @@ config GPIO_LOONGSON_64BIT
> depends on LOONGARCH || COMPILE_TEST
> depends on OF_GPIO
> select GPIO_GENERIC
> + select GPIOLIB_IRQCHIP
> help
> Say yes here to support the GPIO functionality of a number of
> Loongson series of chips. The Loongson GPIO controller supports
> diff --git a/drivers/gpio/gpio-loongson-64bit.c b/drivers/gpio/gpio-loongson-64bit.c
> index 482e64ba9b42..7fb712e101ce 100644
> --- a/drivers/gpio/gpio-loongson-64bit.c
> +++ b/drivers/gpio/gpio-loongson-64bit.c
> @@ -7,6 +7,8 @@
>
> #include <linux/kernel.h>
> #include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/irqdesc.h>
> #include <linux/module.h>
> #include <linux/spinlock.h>
> #include <linux/err.h>
> @@ -14,6 +16,7 @@
> #include <linux/gpio/generic.h>
> #include <linux/platform_device.h>
> #include <linux/bitops.h>
> +#include <linux/reset.h>
> #include <asm/types.h>
>
> enum loongson_gpio_mode {
> @@ -28,6 +31,14 @@ struct loongson_gpio_chip_data {
> unsigned int out_offset;
> unsigned int in_offset;
> unsigned int inten_offset;
> + unsigned int intpol_offset;
> + unsigned int intedge_offset;
> + unsigned int intclr_offset;
> + unsigned int intsts_offset;
> + unsigned int intdual_offset;
> + unsigned int intr_num;
> + irq_flow_handler_t irq_handler;
> + const struct irq_chip *girqchip;
> };
>
> struct loongson_gpio_chip {
> @@ -137,7 +148,140 @@ static int loongson_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
> return platform_get_irq(pdev, offset);
> }
>
> -static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgpio,
> +static void loongson_gpio_irq_ack(struct irq_data *data)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
> + irq_hw_number_t hwirq = irqd_to_hwirq(data);
> +
> + writeb(0x1, lgpio->reg_base + lgpio->chip_data->intclr_offset + hwirq);
> +}
> +
> +static void loongson_gpio_irq_mask(struct irq_data *data)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
> + irq_hw_number_t hwirq = irqd_to_hwirq(data);
> +
> + writeb(0x0, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq);
> +}
> +
> +static void loongson_gpio_irq_unmask(struct irq_data *data)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
> + irq_hw_number_t hwirq = irqd_to_hwirq(data);
> +
> + writeb(0x1, lgpio->reg_base + lgpio->chip_data->inten_offset + hwirq);
> +}
> +
> +static int loongson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
> +{
> + struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
> + struct loongson_gpio_chip *lgpio = to_loongson_gpio_chip(chip);
> + irq_hw_number_t hwirq = irqd_to_hwirq(data);
> + u8 pol = 0, edge = 0, dual = 0;
> +
> + if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
> + edge = 1;
> + dual = 1;
> + irq_set_handler_locked(data, handle_edge_irq);
> + } else {
> + switch (type) {
> + case IRQ_TYPE_LEVEL_HIGH:
> + pol = 1;
> + fallthrough;
> + case IRQ_TYPE_LEVEL_LOW:
> + irq_set_handler_locked(data, handle_level_irq);
> + break;
> +
> + case IRQ_TYPE_EDGE_RISING:
> + pol = 1;
> + fallthrough;
> + case IRQ_TYPE_EDGE_FALLING:
> + edge = 1;
> + irq_set_handler_locked(data, handle_edge_irq);
> + break;
> +
> + default:
> + return -EINVAL;
> + };
> + }
> +
> + writeb(pol, lgpio->reg_base + lgpio->chip_data->intpol_offset + hwirq);
> + writeb(edge, lgpio->reg_base + lgpio->chip_data->intedge_offset + hwirq);
> + writeb(dual, lgpio->reg_base + lgpio->chip_data->intdual_offset + hwirq);
> +
> + return 0;
> +}
> +
> +static void loongson_gpio_ls2k0300_irq_handler(struct irq_desc *desc)
> +{
> + struct loongson_gpio_chip *lgpio = irq_desc_get_handler_data(desc);
> + struct irq_chip *girqchip = irq_desc_get_chip(desc);
> + int i;
> +
> + chained_irq_enter(girqchip, desc);
> +
> + for (i = 0; i < lgpio->chip.gc.ngpio; i++) {
> + /*
> + * For the GPIO controller of 2K0300, interrupts status bits
s/2K0300/LS2K0300/g.
> + * may be wrongly set even if the corresponding interrupt is
> + * disabled. Thus interrupt enable bits are checked along with
> + * status bits to detect interrupts reliably.
> + */
> + if (readb(lgpio->reg_base + lgpio->chip_data->intsts_offset + i) &&
> + readb(lgpio->reg_base + lgpio->chip_data->inten_offset + i))
> + generic_handle_domain_irq(lgpio->chip.gc.irq.domain, i);
> + }
> +
> + chained_irq_exit(girqchip, desc);
> +}
> +
> +static const struct irq_chip loongson_gpio_ls2k0300_irqchip = {
> + .irq_ack = loongson_gpio_irq_ack,
> + .irq_mask = loongson_gpio_irq_mask,
> + .irq_unmask = loongson_gpio_irq_unmask,
> + .irq_set_type = loongson_gpio_irq_set_type,
> + .flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE,
> + GPIOCHIP_IRQ_RESOURCE_HELPERS,
> +};
> +
> +static int loongson_gpio_init_irqchip(struct platform_device *pdev,
> + struct loongson_gpio_chip *lgpio)
> +{
> + const struct loongson_gpio_chip_data *data = lgpio->chip_data;
> + struct gpio_chip *chip = &lgpio->chip.gc;
> + int i;
> +
> + chip->irq.default_type = IRQ_TYPE_NONE;
> + chip->irq.handler = handle_bad_irq;
> + chip->irq.parent_handler = data->irq_handler;
> + chip->irq.parent_handler_data = lgpio;
> + gpio_irq_chip_set_chip(&chip->irq, data->girqchip);
> +
> + chip->irq.num_parents = data->intr_num;
> + chip->irq.parents = devm_kcalloc(&pdev->dev, data->intr_num,
> + sizeof(*chip->irq.parents), GFP_KERNEL);
> + if (!chip->parent)
> + return -ENOMEM;
> +
> + for (i = 0; i < data->intr_num; i++) {
> + chip->irq.parents[i] = platform_get_irq(pdev, i);
> + if (chip->irq.parents[i] < 0)
> + return dev_err_probe(&pdev->dev, chip->irq.parents[i],
> + "failed to get IRQ %d\n", i);
> + }
> +
> + for (i = 0; i < data->intr_num; i++) {
> + writeb(0x0, lgpio->reg_base + data->inten_offset + i);
> + writeb(0x1, lgpio->reg_base + data->intclr_offset + i);
> + }
> +
> + return 0;
> +}
> +
> +static int loongson_gpio_init(struct platform_device *pdev, struct loongson_gpio_chip *lgpio,
> void __iomem *reg_base)
> {
> struct gpio_generic_chip_config config;
> @@ -146,7 +290,7 @@ static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgp
> lgpio->reg_base = reg_base;
> if (lgpio->chip_data->mode == BIT_CTRL_MODE) {
> config = (typeof(config)){
> - .dev = dev,
> + .dev = &pdev->dev,
> .sz = 8,
> .dat = lgpio->reg_base + lgpio->chip_data->in_offset,
> .set = lgpio->reg_base + lgpio->chip_data->out_offset,
> @@ -155,7 +299,7 @@ static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgp
>
> ret = gpio_generic_chip_init(&lgpio->chip, &config);
> if (ret) {
> - dev_err(dev, "unable to init generic GPIO\n");
> + dev_err(&pdev->dev, "unable to init generic GPIO\n");
> return ret;
> }
> } else {
> @@ -164,16 +308,22 @@ static int loongson_gpio_init(struct device *dev, struct loongson_gpio_chip *lgp
> lgpio->chip.gc.get_direction = loongson_gpio_get_direction;
> lgpio->chip.gc.direction_output = loongson_gpio_direction_output;
> lgpio->chip.gc.set = loongson_gpio_set;
> - lgpio->chip.gc.parent = dev;
> + lgpio->chip.gc.parent = &pdev->dev;
> spin_lock_init(&lgpio->lock);
> }
>
> lgpio->chip.gc.label = lgpio->chip_data->label;
> lgpio->chip.gc.can_sleep = false;
> - if (lgpio->chip_data->inten_offset)
> + if (lgpio->chip_data->girqchip) {
> + ret = loongson_gpio_init_irqchip(pdev, lgpio);
> + if (ret)
> + return dev_err_probe(&pdev->dev, ret,
> + "failed to initialize irqchip\n");
One line is enough.
> + } else if (lgpio->chip_data->inten_offset) {
> lgpio->chip.gc.to_irq = loongson_gpio_to_irq;
> + }
>
> - return devm_gpiochip_add_data(dev, &lgpio->chip.gc, lgpio);
> + return devm_gpiochip_add_data(&pdev->dev, &lgpio->chip.gc, lgpio);
> }
>
> static int loongson_gpio_probe(struct platform_device *pdev)
> @@ -181,6 +331,7 @@ static int loongson_gpio_probe(struct platform_device *pdev)
> void __iomem *reg_base;
> struct loongson_gpio_chip *lgpio;
> struct device *dev = &pdev->dev;
> + struct reset_control *rst;
>
> lgpio = devm_kzalloc(dev, sizeof(*lgpio), GFP_KERNEL);
> if (!lgpio)
> @@ -192,7 +343,12 @@ static int loongson_gpio_probe(struct platform_device *pdev)
> if (IS_ERR(reg_base))
> return PTR_ERR(reg_base);
>
> - return loongson_gpio_init(dev, lgpio, reg_base);
> + rst = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL);
> + if (IS_ERR(rst))
> + return dev_err_probe(&pdev->dev, PTR_ERR(rst),
> + "failed to get reset control\n");
One line is enough.
With above changes,
Reviewed-by: Huacai Chen <chenhuacai@...ngson.cn>
> +
> + return loongson_gpio_init(pdev, lgpio, reg_base);
> }
>
> static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = {
> @@ -204,6 +360,23 @@ static const struct loongson_gpio_chip_data loongson_gpio_ls2k_data = {
> .inten_offset = 0x30,
> };
>
> +static const struct loongson_gpio_chip_data loongson_gpio_ls2k0300_data = {
> + .label = "ls2k0300_gpio",
> + .mode = BYTE_CTRL_MODE,
> + .conf_offset = 0x800,
> + .in_offset = 0xa00,
> + .out_offset = 0x900,
> + .inten_offset = 0xb00,
> + .intpol_offset = 0xc00,
> + .intedge_offset = 0xd00,
> + .intclr_offset = 0xe00,
> + .intsts_offset = 0xf00,
> + .intdual_offset = 0xf80,
> + .intr_num = 7,
> + .irq_handler = loongson_gpio_ls2k0300_irq_handler,
> + .girqchip = &loongson_gpio_ls2k0300_irqchip,
> +};
> +
> static const struct loongson_gpio_chip_data loongson_gpio_ls2k0500_data0 = {
> .label = "ls2k0500_gpio",
> .mode = BIT_CTRL_MODE,
> @@ -300,6 +473,10 @@ static const struct of_device_id loongson_gpio_of_match[] = {
> .compatible = "loongson,ls2k-gpio",
> .data = &loongson_gpio_ls2k_data,
> },
> + {
> + .compatible = "loongson,ls2k0300-gpio",
> + .data = &loongson_gpio_ls2k0300_data,
> + },
> {
> .compatible = "loongson,ls2k0500-gpio0",
> .data = &loongson_gpio_ls2k0500_data0,
> --
> 2.50.1
>
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