| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <18915c80-84c3-4a61-a5d2-d40387ec4eb7@intel.com>
Date: Mon, 1 Sep 2025 20:01:57 +0300
From: Adrian Hunter <adrian.hunter@...el.com>
To: Ben Chuang <benchuanggli@...il.com>, <ulf.hansson@...aro.org>
CC: <victor.shih@...esyslogic.com.tw>, <ben.chuang@...esyslogic.com.tw>,
<HL.Liu@...esyslogic.com.tw>, <SeanHY.Chen@...esyslogic.com.tw>,
<victorshihgli@...il.com>, <linux-mmc@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <stable@...r.kernel.org>
Subject: Re: [PATCH 2/2] mmc: sdhci-pci-gli: GL9767: Fix initializing the
UHS-II interface during a power-on
On 01/09/2025 12:42, Ben Chuang wrote:
> From: Ben Chuang <ben.chuang@...esyslogic.com.tw>
>
> According to the power structure of IC hardware design for UHS-II
> interface, reset control and timing must be added to the initialization
> process of powering on the UHS-II interface.
>
> Fixes: 27dd3b82557a ("mmc: sdhci-pci-gli: enable UHS-II mode for GL9767")
> Cc: stable@...r.kernel.org # v6.13+
> Signed-off-by: Ben Chuang <ben.chuang@...esyslogic.com.tw>
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 71 +++++++++++++++++++++++++++++++-
> 1 file changed, 70 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index 3a1de477e9af..85d0d7e6169c 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -283,6 +283,8 @@
> #define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb
> #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6)
> #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1
> +#define PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN BIT(13)
> +#define PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE BIT(14)
>
> #define GLI_MAX_TUNING_LOOP 40
>
> @@ -1179,6 +1181,69 @@ static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable)
> gl9767_vhs_read(pdev);
> }
>
> +static void sdhci_gl9767_uhs2_phy_reset_assert(struct sdhci_host *host)
> +{
> + struct sdhci_pci_slot *slot = sdhci_priv(host);
> + struct pci_dev *pdev = slot->chip->pdev;
> + u32 value;
> +
> + gl9767_vhs_write(pdev);
> + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
> + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
> + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
> + gl9767_vhs_read(pdev);
> +}
> +
> +static void sdhci_gl9767_uhs2_phy_reset_deassert(struct sdhci_host *host)
> +{
> + struct sdhci_pci_slot *slot = sdhci_priv(host);
> + struct pci_dev *pdev = slot->chip->pdev;
> + u32 value;
> +
> + gl9767_vhs_write(pdev);
> + pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
> + value |= PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
Maybe add a small comment about PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE
and PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN being updated separately.
> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
> + value &= ~PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
> + pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
> + gl9767_vhs_read(pdev);
> +}
sdhci_gl9767_uhs2_phy_reset_assert() and sdhci_gl9767_uhs2_phy_reset_deassert()
are fairly similar. Maybe consider:
static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert)
{
struct sdhci_pci_slot *slot = sdhci_priv(host);
struct pci_dev *pdev = slot->chip->pdev;
u32 value, set, clr;
if (assert) {
set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
} else {
set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE;
clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN;
}
gl9767_vhs_write(pdev);
pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value);
value |= set;
pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
value &= ~clr;
pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value);
gl9767_vhs_read(pdev);
}
> +
> +static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd)
> +{
> + u8 pwr = 0;
> +
> + if (mode != MMC_POWER_OFF) {
> + pwr = sdhci_get_vdd_value(vdd);
> + if (!pwr)
> + WARN(1, "%s: Invalid vdd %#x\n",
> + mmc_hostname(host->mmc), vdd);
> + pwr |= SDHCI_VDD2_POWER_180;
> + }
> +
> + if (host->pwr == pwr)
> + return;
> +
> + host->pwr = pwr;
> +
> + if (pwr == 0) {
> + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> + } else {
> + sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
> +
> + pwr |= SDHCI_POWER_ON;
> + sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL);
> + mdelay(5);
Can be mmc_delay(5)
> +
> + sdhci_gl9767_uhs2_phy_reset_assert(host);
> + pwr |= SDHCI_VDD2_POWER_ON;
> + sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
> + mdelay(5);
Can be mmc_delay(5)
> + }
> +}
> +
> static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
> {
> struct sdhci_pci_slot *slot = sdhci_priv(host);
> @@ -1205,6 +1270,10 @@ static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
> }
>
> sdhci_enable_clk(host, clk);
> +
> + if (mmc_card_uhs2(host->mmc))
> + sdhci_gl9767_uhs2_phy_reset_deassert(host);
> +
> gl9767_set_low_power_negotiation(pdev, true);
> }
>
> @@ -1476,7 +1545,7 @@ static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode,
> gl9767_vhs_read(pdev);
>
> sdhci_gli_overcurrent_event_enable(host, false);
> - sdhci_uhs2_set_power(host, mode, vdd);
> + __gl9767_uhs2_set_power(host, mode, vdd);
> sdhci_gli_overcurrent_event_enable(host, true);
> } else {
> gl9767_vhs_write(pdev);
Powered by blists - more mailing lists