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Message-ID: <aLXbyJ/PcHkpYSos@hu-mohdayaa-hyd.qualcomm.com>
Date: Mon, 1 Sep 2025 23:15:44 +0530
From: Mohd Ayaan Anwar <quic_mohdayaa@...cinc.com>
To: Andrew Lunn <andrew@...n.ch>
CC: Wasim Nazir <quic_wasimn@...cinc.com>,
Bjorn Andersson
<andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, Rob Herring
<robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley
<conor+dt@...nel.org>,
Richard Cochran <richardcochran@...il.com>,
<linux-arm-msm@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <netdev@...r.kernel.org>,
<kernel@...cinc.com>, <kernel@....qualcomm.com>
Subject: Re: [PATCH 3/8] arm64: dts: qcom: sa8775p: Add ethernet card for
ride & ride-r3
On Wed, May 07, 2025 at 04:23:52PM +0200, Andrew Lunn wrote:
> > +ðernet0 {
> > + phy-handle = <&sgmii_phy0>;
> > + phy-mode = "sgmii";
> > +
> > + pinctrl-0 = <ðernet0_default>;
> > + pinctrl-names = "default";
> > +
> > + snps,mtl-rx-config = <&mtl_rx_setup>;
> > + snps,mtl-tx-config = <&mtl_tx_setup>;
> > + snps,ps-speed = <1000>;
>
> SGMII can only go up to 1000, so why is this property needed?
>
That's true. This shouldn't be required.
> > +ðernet0 {
> > + phy-handle = <&hsgmii_phy0>;
> > + phy-mode = "2500base-x";
> > +
> > + pinctrl-0 = <ðernet0_default>;
> > + pinctrl-names = "default";
> > +
> > + snps,mtl-rx-config = <&mtl_rx_setup>;
> > + snps,mtl-tx-config = <&mtl_tx_setup>;
> > + snps,ps-speed = <1000>;
>
> This looks odd. 2500Base-X, yet 1000?
>
> Andrew
Just to give some background, this board is using the infamous OCSGMII
mode. But you are correct, the "snps,ps-speed" property is not required
here. The qcom-ethqos driver is agnostic to it as the MAC speed is set
using PCS AN during mac_link_up:
stmmac_mac_link_up -> fix_mac_speed -> ethqos_configure_sgmii.
We will remove it in the next revision of [0]. I also noticed this
redundant property in a few other places and will submit separate
cleanup patches for those as well.
Ayaan
---
[0] https://lore.kernel.org/all/20250826-lemans-evk-bu-v1-3-08016e0d3ce5@oss.qualcomm.com/
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