| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250901224327.3429099-2-prabhakar.mahadev-lad.rj@bp.renesas.com>
Date: Mon, 1 Sep 2025 23:43:14 +0100
From: Prabhakar <prabhakar.csengg@...il.com>
To: Clément Léger <clement.leger@...tlin.com>,
Andrew Lunn <andrew+netdev@...n.ch>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Philipp Zabel <p.zabel@...gutronix.de>,
Geert Uytterhoeven <geert+renesas@...der.be>,
Magnus Damm <magnus.damm@...il.com>,
Wolfram Sang <wsa+renesas@...g-engineering.com>
Cc: linux-renesas-soc@...r.kernel.org,
netdev@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Prabhakar <prabhakar.csengg@...il.com>,
Biju Das <biju.das.jz@...renesas.com>,
Fabrizio Castro <fabrizio.castro.jz@...esas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: [PATCH net-next 01/10] dt-bindings: net: pcs: renesas,rzn1-miic: Document RZ/T2H and RZ/N2H SoCs
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
Extend the RZN1 MIIC device-tree binding schema to cover the RZ/T2H
and RZ/N2H SoCs. These SoCs have a MIIC converter similar to RZ/N1, but
with some differences:
- RZ/T2H has two reset lines; RZ/N1 has none.
- RZ/N1 supports 5 MIIC ports, whereas RZ/T2H supports 4 ports.
- On RZ/N1, MIIC ports can be mapped to various endpoints such as RTOS
MAC ports, switch ports, EtherCAT ports, SERCOS ports, HSR ports, or
fixed PHY ports (covering PHY input indices 0-13). On RZ/T2H, ports
can connect to EtherCAT slave ports, Ethernet switch ports, or GMAC
ports (mapped to PHY input indices 0-8).
- There are register bit differences between the SoCs, and RZ/N1 has
additional registers currently unused by the driver.
- On RZ/T2H, the switch is connected to GMAC0 whereas on RZ/N1 the
switch can be connected to GMAC2/HW-RTOS GMAC.
To accommodate these differences, a new generic compatible string
`renesas,rzt2h-miic` is introduced for both RZ/T2H and RZ/N2H variants.
The DT schema is updated to validate these differences and ensure proper
port and reset configurations per SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
---
.../bindings/net/pcs/renesas,rzn1-miic.yaml | 171 +++++++++++++-----
include/dt-bindings/net/pcs-rzt2h-miic.h | 23 +++
2 files changed, 148 insertions(+), 46 deletions(-)
create mode 100644 include/dt-bindings/net/pcs-rzt2h-miic.h
diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
index 2d33bbab7163..832a49877a29 100644
--- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
+++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml
@@ -4,13 +4,14 @@
$id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Renesas RZ/N1 MII converter
+title: Renesas RZ/{N1, N2H, T2H} MII converter
maintainers:
- Clément Léger <clement.leger@...tlin.com>
+ - Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
description: |
- This MII converter is present on the Renesas RZ/N1 SoC family. It is
+ This MII converter is present on the Renesas RZ/{N1, N2H, T2H} SoC families. It is
responsible to do MII passthrough or convert it to RMII/RGMII.
properties:
@@ -21,10 +22,17 @@ properties:
const: 0
compatible:
- items:
- - enum:
- - renesas,r9a06g032-miic
- - const: renesas,rzn1-miic
+ oneOf:
+ - items:
+ - enum:
+ - renesas,r9a06g032-miic
+ - const: renesas,rzn1-miic
+
+ - items:
+ - enum:
+ - renesas,r9a09g077-miic # RZ/T2H
+ - renesas,r9a09g087-miic # RZ/N2H
+ - const: renesas,rzt2h-miic
reg:
maxItems: 1
@@ -43,11 +51,20 @@ properties:
- const: rmii_ref
- const: hclk
+ resets:
+ items:
+ - description: Converter register reset
+ - description: Converter reset
+
+ reset-names:
+ items:
+ - const: rst
+ - const: crst
+
renesas,miic-switch-portin:
description: MII Switch PORTIN configuration. This value should use one of
the values defined in dt-bindings/net/pcs-rzn1-miic.h.
$ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2]
power-domains:
maxItems: 1
@@ -60,11 +77,11 @@ patternProperties:
properties:
reg:
description: MII Converter port number.
- enum: [1, 2, 3, 4, 5]
renesas,miic-input:
description: Converter input port configuration. This value should use
- one of the values defined in dt-bindings/net/pcs-rzn1-miic.h.
+ one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC
+ and include/dt-bindings/net/pcs-rzt2h-miic.h for RZ/{T2H, N2H} SoCs.
$ref: /schemas/types.yaml#/definitions/uint32
required:
@@ -73,47 +90,109 @@ patternProperties:
additionalProperties: false
- allOf:
- - if:
- properties:
- reg:
- const: 1
- then:
- properties:
- renesas,miic-input:
- const: 0
- - if:
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rzn1-miic
+ then:
+ properties:
+ renesas,miic-switch-portin:
+ enum: [1, 2]
+ patternProperties:
+ "^mii-conv@[0-5]$":
properties:
reg:
- const: 2
- then:
- properties:
- renesas,miic-input:
- enum: [1, 11]
- - if:
- properties:
- reg:
- const: 3
- then:
- properties:
- renesas,miic-input:
- enum: [7, 10]
- - if:
+ enum: [1, 2, 3, 4, 5]
+ resets: false
+ reset-names: false
+ allOf:
+ - if:
+ properties:
+ reg:
+ const: 1
+ then:
+ properties:
+ renesas,miic-input:
+ const: 0
+ - if:
+ properties:
+ reg:
+ const: 2
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [1, 11]
+ - if:
+ properties:
+ reg:
+ const: 3
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [7, 10]
+ - if:
+ properties:
+ reg:
+ const: 4
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [4, 6, 9, 13]
+ - if:
+ properties:
+ reg:
+ const: 5
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [3, 5, 8, 12]
+ else:
+ properties:
+ renesas,miic-switch-portin:
+ const: 0
+ required:
+ - resets
+ - reset-names
+ patternProperties:
+ "^mii-conv@[0-5]$":
properties:
reg:
- const: 4
- then:
- properties:
- renesas,miic-input:
- enum: [4, 6, 9, 13]
- - if:
- properties:
- reg:
- const: 5
- then:
- properties:
- renesas,miic-input:
- enum: [3, 5, 8, 12]
+ enum: [0, 1, 2, 3]
+ allOf:
+ - if:
+ properties:
+ reg:
+ const: 0
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [0, 3, 6]
+ - if:
+ properties:
+ reg:
+ const: 1
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [1, 4, 7]
+ - if:
+ properties:
+ reg:
+ const: 2
+ then:
+ properties:
+ renesas,miic-input:
+ enum: [2, 5, 8]
+ - if:
+ properties:
+ reg:
+ const: 3
+ then:
+ properties:
+ renesas,miic-input:
+ const: 1
required:
- '#address-cells'
diff --git a/include/dt-bindings/net/pcs-rzt2h-miic.h b/include/dt-bindings/net/pcs-rzt2h-miic.h
new file mode 100644
index 000000000000..c1f35fc0f1cd
--- /dev/null
+++ b/include/dt-bindings/net/pcs-rzt2h-miic.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Renesas Electronics Corporation.
+ */
+
+#ifndef _DT_BINDINGS_PCS_RZT2H_ETHSS
+#define _DT_BINDINGS_PCS_RZT2H_ETHSS
+
+/*
+ * Refer to the datasheet Internal Connection of Ethernet
+ * Ports to check the available combination
+ */
+#define ETHSS_GMAC0_PORT 0
+#define ETHSS_GMAC1_PORT 1
+#define ETHSS_GMAC2_PORT 2
+#define ETHSS_ETHERCAT_PORT0 3
+#define ETHSS_ETHERCAT_PORT1 4
+#define ETHSS_ETHERCAT_PORT2 5
+#define ETHSS_SWITCH_PORT0 6
+#define ETHSS_SWITCH_PORT1 7
+#define ETHSS_SWITCH_PORT2 8
+
+#endif
--
2.51.0
Powered by blists - more mailing lists