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Message-ID: <20250901055922.1553550-7-jacky_chou@aspeedtech.com>
Date: Mon, 1 Sep 2025 13:59:18 +0800
From: Jacky Chou <jacky_chou@...eedtech.com>
To: <linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <bhelgaas@...gle.com>,
<lpieralisi@...nel.org>, <kwilczynski@...nel.org>, <mani@...nel.org>,
<robh@...nel.org>, <krzk+dt@...nel.org>, <conor+dt@...nel.org>,
<joel@....id.au>, <andrew@...econstruct.com.au>, <vkoul@...nel.org>,
<kishon@...nel.org>, <linus.walleij@...aro.org>, <p.zabel@...gutronix.de>,
<linux-aspeed@...ts.ozlabs.org>, <linux-arm-kernel@...ts.infradead.org>,
<linux-phy@...ts.infradead.org>, <openbmc@...ts.ozlabs.org>,
<linux-gpio@...r.kernel.org>
CC: <jacky_chou@...eedtech.com>
Subject: [PATCH v3 06/10] ARM: dts: aspeed-g6: Add PCIe RC and PCIe PHY node
The AST2600 has one PCIe RC and add the PCIe PHY for RC.
Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
---
arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 56 +++++++++++++++++++++++++
1 file changed, 56 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
index 8ed715bd53aa..a1ccc141647f 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi
@@ -379,6 +379,62 @@ rng: hwrng@...e2524 {
quality = <100>;
};
+ pcie_phy1: phy@...ed200 {
+ compatible = "aspeed,ast2600-pcie-phy";
+ reg = <0x1e6ed200 0x100>;
+ #phy-cells = <0>;
+ };
+
+ pcie0: pcie@...70000 {
+ compatible = "aspeed,ast2600-pcie";
+ device_type = "pci";
+ reg = <0x1e770000 0x100>;
+ linux,pci-domain = <0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+ bus-range = <0x80 0xff>;
+
+ ranges = <0x01000000 0x0 0x00018000 0x00018000 0x0 0x00008000
+ 0x02000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
+
+ status = "disabled";
+
+ resets = <&syscon ASPEED_RESET_H2X>;
+ reset-names = "h2x";
+
+ #interrupt-cells = <1>;
+ msi-parent = <&pcie0>;
+ msi-controller;
+
+ aspeed,ahbc = <&ahbc>;
+
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+ <0 0 0 2 &pcie_intc0 1>,
+ <0 0 0 3 &pcie_intc0 2>,
+ <0 0 0 4 &pcie_intc0 3>;
+ pcie_intc0: interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ };
+
+ pcie@8,0 {
+ reg = <0x804000 0 0 0 0>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ resets = <&syscon ASPEED_RESET_PCIE_RC_O>;
+ reset-names = "perst";
+ clocks = <&syscon ASPEED_CLK_GATE_BCLK>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pcierc1_default>;
+ phys = <&pcie_phy1>;
+ ranges;
+ };
+ };
+
gfx: display@...e6000 {
compatible = "aspeed,ast2600-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;
--
2.43.0
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