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Message-Id: <20250901113022.3812-1-luxu.kernel@bytedance.com> Date: Mon, 1 Sep 2025 19:30:18 +0800 From: Xu Lu <luxu.kernel@...edance.com> To: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org, paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr, ajones@...tanamicro.com, brs@...osinc.com Cc: devicetree@...r.kernel.org, linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org, apw@...onical.com, joe@...ches.com, Xu Lu <luxu.kernel@...edance.com> Subject: [PATCH 0/4] riscv: Add Zalasr ISA exntesion support This patch adds support for the Zalasr ISA extension, which supplies the real load acquire/store release instructions. The specification can be found here: https://github.com/riscv/riscv-zalasr/blob/main/chapter2.adoc This patch seires has been tested with ltp on Qemu with Brensan's zalasr support patch[1]. Some false positive spacing error happens during patch checking. Thus I CCed maintainers of checkpatch.pl as well. [1] https://lore.kernel.org/all/CAGPSXwJEdtqW=nx71oufZp64nK6tK=0rytVEcz4F-gfvCOXk2w@mail.gmail.com/ Xu Lu (4): riscv: add ISA extension parsing for Zalasr dt-bindings: riscv: Add Zalasr ISA extension description riscv: Instroduce Zalasr instructions riscv: Use Zalasr for smp_load_acquire/smp_store_release .../devicetree/bindings/riscv/extensions.yaml | 5 ++ arch/riscv/include/asm/barrier.h | 79 ++++++++++++++++--- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/include/asm/insn-def.h | 79 +++++++++++++++++++ arch/riscv/kernel/cpufeature.c | 1 + 5 files changed, 154 insertions(+), 11 deletions(-) -- 2.20.1
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