linux-kernel - [PATCH RESEND 0/2] riscv: mm: Some optimizations for tlb flush

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Message-Id: <20250901114141.5438-1-luxu.kernel@bytedance.com>
Date: Mon,  1 Sep 2025 19:41:39 +0800
From: Xu Lu <luxu.kernel@...edance.com>
To: paul.walmsley@...ive.com,
	palmer@...belt.com,
	aou@...s.berkeley.edu,
	alex@...ti.fr
Cc: linux-riscv@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	apw@...onical.com,
	joe@...ches.com,
	Xu Lu <luxu.kernel@...edance.com>
Subject: [PATCH RESEND 0/2] riscv: mm: Some optimizations for tlb flush

Some optimizations for tlb flush on RISC-V smp:
1. Apply Svinval in update_mmu_cache() to avoid flushing irrelevant tlb
entries.
2. Clear bit of current cpu in mm_cpumask after local_flush_tlb_all_asid()
to avoid potential IPIs in the future.

We saw the number of IPI reduced from ~98k to 268 on mmapstress01
benchmark.

Some false positive spacing error happens during patch checking. Thus I
CCed maintainers of checkpatch.pl as well.

Xu Lu (2):
  riscv: mm: Apply svinval in update_mmu_cache()
  riscv: mm: Clear cpu in mm_cpumask after local_flush_tlb_all_asid

 arch/riscv/include/asm/pgtable.h  | 16 +++++++-
 arch/riscv/include/asm/tlbflush.h | 23 +++++++++++
 arch/riscv/mm/tlbflush.c          | 64 ++++++++++++-------------------
 3 files changed, 63 insertions(+), 40 deletions(-)

-- 
2.20.1