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Message-ID: <aLWVvuGrxL2OQRSd@vaman>
Date: Mon, 1 Sep 2025 18:16:54 +0530
From: Vinod Koul <vkoul@...nel.org>
To: Wenbin Yao <wenbin.yao@....qualcomm.com>
Cc: Kishon Vijay Abraham I <kishon@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Bjorn Helgaas <bhelgaas@...gle.com>,
	Lorenzo Pieralisi <lpieralisi@...nel.org>,
	Krzysztof WilczyƄski <kwilczynski@...nel.org>,
	Manivannan Sadhasivam <mani@...nel.org>,
	Bjorn Andersson <andersson@...nel.org>,
	linux-arm-msm@...r.kernel.org, linux-phy@...ts.infradead.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	linux-pci@...r.kernel.org, konrad.dybcio@....qualcomm.com,
	qiang.yu@....qualcomm.com,
	Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
Subject: Re: [PATCH v3 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy:
 Document the Glymur QMP PCIe PHY

On 25-08-25, 23:01, Wenbin Yao wrote:
> From: Prudhvi Yarlagadda <quic_pyarlaga@...cinc.com>
> 
> The fifth PCIe instance on Glymur has a Gen5 4-lane PHY. Document it as a
> separate compatible.

This does not apply for me, please rebase and send

-- 
~Vinod

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