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Message-Id: <20250902042143.1010-1-jie.gan@oss.qualcomm.com>
Date: Tue, 2 Sep 2025 12:21:43 +0800
From: Jie Gan <jie.gan@....qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@....com>,
Mike Leach <mike.leach@...aro.org>,
James Clark <james.clark@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Tingwei Zhang <tingwei.zhang@....qualcomm.com>,
Mao Jinlong <jinlong.mao@....qualcomm.com>,
Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>,
Tao Zhang <tao.zhang@....qualcomm.com>
Cc: coresight@...ts.linaro.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org
Subject: [PATCH v1] dt-binding: Update oss email address for Coresight documents
Update the OSS email addresses across all Coresight documents, as the
previous addresses have been deprecated.
Signed-off-by: Jie Gan <jie.gan@....qualcomm.com>
---
.../sysfs-bus-coresight-devices-dummy-source | 4 +-
.../testing/sysfs-bus-coresight-devices-tpdm | 56 +++++++++----------
.../arm/arm,coresight-dummy-sink.yaml | 2 +-
.../arm/arm,coresight-dummy-source.yaml | 2 +-
.../bindings/arm/qcom,coresight-ctcu.yaml | 6 +-
.../arm/qcom,coresight-remote-etm.yaml | 4 +-
.../bindings/arm/qcom,coresight-tnoc.yaml | 2 +-
.../bindings/arm/qcom,coresight-tpda.yaml | 4 +-
.../bindings/arm/qcom,coresight-tpdm.yaml | 4 +-
9 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
index 0830661ef656..efd9f96d6eca 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-dummy-source
@@ -1,7 +1,7 @@
What: /sys/bus/coresight/devices/dummy_source<N>/enable_source
Date: Dec 2024
KernelVersion: 6.14
-Contact: Mao Jinlong <quic_jinlmao@...cinc.com>
+Contact: Mao Jinlong <jinlong.mao@....qualcomm.com>
Description: (RW) Enable/disable tracing of dummy source. A sink should be activated
before enabling the source. The path of coresight components linking
the source to the sink is configured and managed automatically by the
@@ -10,6 +10,6 @@ Description: (RW) Enable/disable tracing of dummy source. A sink should be activ
What: /sys/bus/coresight/devices/dummy_source<N>/traceid
Date: Dec 2024
KernelVersion: 6.14
-Contact: Mao Jinlong <quic_jinlmao@...cinc.com>
+Contact: Mao Jinlong <jinlong.mao@....qualcomm.com>
Description: (R) Show the trace ID that will appear in the trace stream
coming from this trace entity.
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
index a341b08ae70b..86e508a1b409 100644
--- a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
@@ -1,7 +1,7 @@
What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
Date: January 2023
KernelVersion: 6.2
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(Write) Run integration test for tpdm. Integration test
will generate test data for tpdm. It can help to make
@@ -15,7 +15,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/reset_dataset
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(Write) Reset the dataset of the tpdm.
@@ -25,7 +25,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_type
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the trigger type of the DSB for tpdm.
@@ -36,7 +36,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_ts
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the trigger timestamp of the DSB for tpdm.
@@ -47,7 +47,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_mode
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the programming mode of the DSB for tpdm.
@@ -61,7 +61,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_idx
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the index number of the edge detection for the DSB
subunit TPDM. Since there are at most 256 edge detections, this
@@ -70,7 +70,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_val
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
Write a data to control the edge detection corresponding to
the index number. Before writing data to this sysfs file,
@@ -86,7 +86,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/ctrl_mask
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
Write a data to mask the edge detection corresponding to the index
number. Before writing data to this sysfs file, "ctrl_idx" should
@@ -98,21 +98,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcr[0:15]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
Read a set of the edge control value of the DSB in TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_edge/edcmr[0:7]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
Read a set of the edge control mask of the DSB in TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpr[0:7]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the value of the trigger pattern for the DSB
subunit TPDM.
@@ -120,7 +120,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_trig_patt/xpmr[0:7]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the mask of the trigger pattern for the DSB
subunit TPDM.
@@ -128,21 +128,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:7]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the value of the pattern for the DSB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:7]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the mask of the pattern for the DSB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/enable_ts
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(Write) Set the pattern timestamp of DSB tpdm. Read
the pattern timestamp of DSB tpdm.
@@ -154,7 +154,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/set_type
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(Write) Set the pattern type of DSB tpdm. Read
the pattern type of DSB tpdm.
@@ -166,7 +166,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_msr/msr[0:31]
Date: March 2023
KernelVersion: 6.7
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the MSR(mux select register) for the DSB subunit
TPDM.
@@ -174,7 +174,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_mode
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description: (Write) Set the data collection mode of CMB tpdm. Continuous
change creates CMB data set elements on every CMBCLK edge.
Trace-on-change creates CMB data set elements only when a new
@@ -188,7 +188,7 @@ Description: (Write) Set the data collection mode of CMB tpdm. Continuous
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpr[0:1]
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the value of the trigger pattern for the CMB
subunit TPDM.
@@ -196,7 +196,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_patt/xpmr[0:1]
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the mask of the trigger pattern for the CMB
subunit TPDM.
@@ -204,21 +204,21 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpr[0:1]
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the value of the pattern for the CMB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/dsb_patt/tpmr[0:1]
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the mask of the pattern for the CMB subunit TPDM.
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_patt/enable_ts
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(Write) Set the pattern timestamp of CMB tpdm. Read
the pattern timestamp of CMB tpdm.
@@ -230,7 +230,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_trig_ts
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the trigger timestamp of the CMB for tpdm.
@@ -241,7 +241,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_ts_all
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Read or write the status of timestamp upon all interface.
Only value 0 and 1 can be written to this node. Set this node to 1 to request
@@ -253,7 +253,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/cmb_msr/msr[0:31]
Date: January 2024
KernelVersion: 6.9
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the MSR(mux select register) for the CMB subunit
TPDM.
@@ -261,7 +261,7 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_trig_lane
Date: Feb 2025
KernelVersion 6.15
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get which lane participates in the output pattern
match cross trigger mechanism for the MCMB subunit TPDM.
@@ -269,6 +269,6 @@ Description:
What: /sys/bus/coresight/devices/<tpdm-name>/mcmb_lanes_select
Date: Feb 2025
KernelVersion 6.15
-Contact: Jinlong Mao (QUIC) <quic_jinlmao@...cinc.com>, Tao Zhang (QUIC) <quic_taozha@...cinc.com>
+Contact: Jinlong Mao <jinlong.mao@....qualcomm.com>, Tao Zhang <tao.zhang@....qualcomm.com>
Description:
(RW) Set/Get the enablement of the individual lane.
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
index 08b89b62c505..deaadf1ca1aa 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-sink.yaml
@@ -31,7 +31,7 @@ maintainers:
- Mike Leach <mike.leach@...aro.org>
- Suzuki K Poulose <suzuki.poulose@....com>
- James Clark <james.clark@...aro.org>
- - Mao Jinlong <quic_jinlmao@...cinc.com>
+ - Mao Jinlong <jinlong.mao@....qualcomm.com>
- Hao Zhang <quic_hazha@...cinc.com>
properties:
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
index 742dc4e25d3b..b29274f6d5c7 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-dummy-source.yaml
@@ -30,7 +30,7 @@ maintainers:
- Mike Leach <mike.leach@...aro.org>
- Suzuki K Poulose <suzuki.poulose@....com>
- James Clark <james.clark@...aro.org>
- - Mao Jinlong <quic_jinlmao@...cinc.com>
+ - Mao Jinlong <jinlong.mao@....qualcomm.com>
- Hao Zhang <quic_hazha@...cinc.com>
properties:
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
index 843b52eaf872..6f713d20833f 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-ctcu.yaml
@@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: CoreSight TMC Control Unit
maintainers:
- - Yuanfang Zhang <quic_yuanfang@...cinc.com>
- - Mao Jinlong <quic_jinlmao@...cinc.com>
- - Jie Gan <quic_jiegan@...cinc.com>
+ - Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>
+ - Mao Jinlong <jinlong.mao@....qualcomm.com>
+ - Jie Gan <jie.gan@....qualcomm.com>
description: |
The Trace Memory Controller(TMC) is used for Embedded Trace Buffer(ETB),
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
index 4fd5752978cd..c68764d759ce 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-remote-etm.yaml
@@ -7,8 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Coresight Remote ETM(Embedded Trace Macrocell)
maintainers:
- - Jinlong Mao <quic_jinlmao@...cinc.com>
- - Tao Zhang <quic_taozha@...cinc.com>
+ - Jinlong Mao <jinlong.mao@....qualcomm.com>
+ - Tao Zhang <tao.zhang@....qualcomm.com>
description:
Support for ETM trace collection on remote processor using coresight
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
index 9d1c93a9ade3..ef648a15b806 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tnoc.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Trace Network On Chip - TNOC
maintainers:
- - Yuanfang Zhang <quic_yuanfang@...cinc.com>
+ - Yuanfang Zhang <yuanfang.zhang@....qualcomm.com>
description: >
The Trace Network On Chip (TNOC) is an integration hierarchy hardware
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
index 5ed40f21b8eb..bab80823f0f6 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpda.yaml
@@ -33,8 +33,8 @@ description: |
to sink.
maintainers:
- - Mao Jinlong <quic_jinlmao@...cinc.com>
- - Tao Zhang <quic_taozha@...cinc.com>
+ - Mao Jinlong <jinlong.mao@....qualcomm.com>
+ - Tao Zhang <tao.zhang@....qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
diff --git a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
index 7c0acc1f25c5..33ec83901651 100644
--- a/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
+++ b/Documentation/devicetree/bindings/arm/qcom,coresight-tpdm.yaml
@@ -19,8 +19,8 @@ description: |
sources and send it to a TPDA for packetization, timestamping, and funneling.
maintainers:
- - Mao Jinlong <quic_jinlmao@...cinc.com>
- - Tao Zhang <quic_taozha@...cinc.com>
+ - Mao Jinlong <jinlong.mao@....qualcomm.com>
+ - Tao Zhang <tao.zhang@....qualcomm.com>
# Need a custom select here or 'arm,primecell' will match on lots of nodes
select:
--
2.34.1
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