linux-kernel - Re: [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets

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Message-ID: <CAMuHMdUmi=pp10=_WNTwbuH-PYknbFyP9iBcQDB+tNKVEXgLpA@mail.gmail.com>
Date: Tue, 2 Sep 2025 15:27:18 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: Biju <biju.das.au@...il.com>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Biju Das <biju.das.jz@...renesas.com>, linux-renesas-soc@...r.kernel.org, 
	linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 02/11] clk: renesas: r9a09g047: Add USB3.0 clocks/resets

Hi Biju,

On Wed, 20 Aug 2025 at 19:18, Biju <biju.das.au@...il.com> wrote:
> From: Biju Das <biju.das.jz@...renesas.com>
>
> Add USB3.0 clock and reset entries.
>
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>

Thanks for your patch!

> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -16,7 +16,7 @@
>
>  enum clk_ids {
>         /* Core Clock Outputs exported to DT */
> -       LAST_DT_CORE_CLK = R9A09G047_GBETH_1_CLK_PTP_REF_I,
> +       LAST_DT_CORE_CLK = R9A09G047_USB3_0_CLKCORE,
>
>         /* External Input Clocks */
>         CLK_AUDIO_EXTAL,
> @@ -181,6 +181,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
>                   CLK_PLLETH_DIV_125_FIX, 1, 1),
>         DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G047_GBETH_1_CLK_PTP_REF_I,
>                   CLK_PLLETH_DIV_125_FIX, 1, 1),
> +       DEF_FIXED("usb30_ref_alt_clk_p", R9A09G047_USB3_0_REF_ALT_CLK_P, CLK_QEXTAL, 1, 1),
> +       DEF_FIXED("usb30_core_clk", R9A09G047_USB3_0_CLKCORE, CLK_QEXTAL, 1, 1),

"usb3_0_..." for both, to match the public define and the clock diagram.

>  };
>
>  static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> @@ -276,6 +278,10 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
>                                                 BUS_MSTOP(8, BIT(4))),
>         DEF_MOD("sdhi_2_aclk",                  CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14,
>                                                 BUS_MSTOP(8, BIT(4))),
> +       DEF_MOD("usb30_aclk",                   CLK_PLLDTY_DIV8, 10, 15, 5, 15,
> +                                               BUS_MSTOP(7, BIT(12))),
> +       DEF_MOD("usb30_pclk_usbtst",            CLK_PLLDTY_ACPU_DIV4, 11, 0, 5, 16,
> +                                               BUS_MSTOP(7, BIT(14))),

"usb3_0_..." for both.
I cannot verify the actual clock bits, but they do lie in the empty
number space. And apparently the censor team forgot to scrub the
MSTOP bits ;-)

>         DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24,
>                                                 BUS_MSTOP(8, BIT(5)), 1),
>         DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25,
> @@ -352,6 +358,7 @@ static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>         DEF_RST(10, 7, 4, 24),          /* SDHI_0_IXRST */
>         DEF_RST(10, 8, 4, 25),          /* SDHI_1_IXRST */
>         DEF_RST(10, 9, 4, 26),          /* SDHI_2_IXRST */
> +       DEF_RST(10, 10, 4, 27),         /* USB30_ARESETN */

I cannot verify the actual reset bits, but they do lie in the empty
number space.
USB3_0_ARESETN, for consistency with the clocks?

>         DEF_RST(11, 0, 5, 1),           /* GBETH_0_ARESETN_I */
>         DEF_RST(11, 1, 5, 2),           /* GBETH_1_ARESETN_I */
>         DEF_RST(12, 5, 5, 22),          /* CRU_0_PRESETN */

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds