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Message-ID: <f2ee23526349a0674149c969a2176c906e529402.1756825388.git.michal.simek@amd.com>
Date: Tue, 2 Sep 2025 17:03:10 +0200
From: Michal Simek <michal.simek@....com>
To: <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
<michal.simek@...inx.com>, <git@...inx.com>
CC: Conor Dooley <conor+dt@...nel.org>, Krzysztof Kozlowski
<krzk+dt@...nel.org>, Rob Herring <robh@...nel.org>, "open list:OPEN FIRMWARE
AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, "moderated
list:ARM/ZYNQ ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH] arm64: versal-net: Describe L2/L3/LLC caches
Add missing cache layout description.
Signed-off-by: Michal Simek <michal.simek@....com>
---
arch/arm64/boot/dts/xilinx/versal-net.dtsi | 248 +++++++++++++++++++++
1 file changed, 248 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/versal-net.dtsi b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
index c037a7819967..62861138c8f4 100644
--- a/arch/arm64/boot/dts/xilinx/versal-net.dtsi
+++ b/arch/arm64/boot/dts/xilinx/versal-net.dtsi
@@ -104,6 +104,18 @@ cpu0: cpu@0 {
reg = <0>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_00>;
+ l2_00: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
};
cpu100: cpu@100 {
compatible = "arm,cortex-a78";
@@ -112,6 +124,18 @@ cpu100: cpu@100 {
reg = <0x100>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_01>;
+ l2_01: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
};
cpu200: cpu@200 {
compatible = "arm,cortex-a78";
@@ -120,6 +144,18 @@ cpu200: cpu@200 {
reg = <0x200>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_02>;
+ l2_02: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
};
cpu300: cpu@300 {
compatible = "arm,cortex-a78";
@@ -128,6 +164,18 @@ cpu300: cpu@300 {
reg = <0x300>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_03>;
+ l2_03: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_0>;
+ };
};
cpu10000: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -136,6 +184,18 @@ cpu10000: cpu@...00 {
reg = <0x10000>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_10>;
+ l2_10: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_1>;
+ };
};
cpu10100: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -144,6 +204,18 @@ cpu10100: cpu@...00 {
reg = <0x10100>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_11>;
+ l2_11: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_1>;
+ };
};
cpu10200: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -152,6 +224,18 @@ cpu10200: cpu@...00 {
reg = <0x10200>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_12>;
+ l2_12: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_1>;
+ };
};
cpu10300: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -160,6 +244,18 @@ cpu10300: cpu@...00 {
reg = <0x10300>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_13>;
+ l2_13: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_1>;
+ };
};
cpu20000: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -168,6 +264,18 @@ cpu20000: cpu@...00 {
reg = <0x20000>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_20>;
+ l2_20: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_2>;
+ };
};
cpu20100: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -176,6 +284,18 @@ cpu20100: cpu@...00 {
reg = <0x20100>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_21>;
+ l2_21: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_2>;
+ };
};
cpu20200: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -184,6 +304,18 @@ cpu20200: cpu@...00 {
reg = <0x20200>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_22>;
+ l2_22: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_2>;
+ };
};
cpu20300: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -192,6 +324,18 @@ cpu20300: cpu@...00 {
reg = <0x20300>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_23>;
+ l2_23: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_2>;
+ };
};
cpu30000: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -200,6 +344,18 @@ cpu30000: cpu@...00 {
reg = <0x30000>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_30>;
+ l2_30: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_3>;
+ };
};
cpu30100: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -208,6 +364,18 @@ cpu30100: cpu@...00 {
reg = <0x30100>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_31>;
+ l2_31: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_3>;
+ };
};
cpu30200: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -216,6 +384,18 @@ cpu30200: cpu@...00 {
reg = <0x30200>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_32>;
+ l2_32: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_3>;
+ };
};
cpu30300: cpu@...00 {
compatible = "arm,cortex-a78";
@@ -224,7 +404,75 @@ cpu30300: cpu@...00 {
reg = <0x30300>;
operating-points-v2 = <&cpu_opp_table>;
cpu-idle-states = <&CPU_SLEEP_0>;
+ next-level-cache = <&l2_33>;
+ l2_33: l2-cache {
+ compatible = "cache";
+ cache-level = <2>;
+ cache-size = <0x80000>; /* 512kB */
+ cache-line-size = <64>;
+ /* 8 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <1024>;
+ cache-unified;
+ next-level-cache = <&l3_3>;
+ };
+ };
+
+ l3_0: l3-0-cache { /* cluster private */
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <0x200000>; /* 2MB */
+ cache-line-size = <64>;
+ /* 16 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&llc>;
+ };
+
+ l3_1: l3-1-cache { /* cluster private */
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <0x200000>; /* 2MB */
+ cache-line-size = <64>;
+ /* 16 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&llc>;
+ };
+
+ l3_2: l3-2-cache { /* cluster private */
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <0x200000>; /* 2MB */
+ cache-line-size = <64>;
+ /* 16 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&llc>;
+ };
+
+ l3_3: l3-3-cache { /* cluster private */
+ compatible = "cache";
+ cache-level = <3>;
+ cache-size = <0x200000>; /* 2MB */
+ cache-line-size = <64>;
+ /* 16 ways set associativity */
+ /* cache_size / (line_size/associativity) */
+ cache-sets = <2048>;
+ cache-unified;
+ next-level-cache = <&llc>;
+ };
+
+ llc: l4-cache { /* LLC inside CMN */
+ compatible = "cache";
+ cache-level = <4>;
+ cache-size = <0x1000000>; /* 16MB */
+ cache-unified;
};
+
idle-states {
entry-method = "psci";
--
2.43.0
base-commit: 3160658ea2c4dd09a1d68918271177cf55437a8f
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