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Message-ID: <175684726867.1179507.1325689582067833868.robh@kernel.org>
Date: Tue, 2 Sep 2025 16:07:49 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Jacky Chou <jacky_chou@...eedtech.com>
Cc: bhelgaas@...gle.com, linux-kernel@...r.kernel.org, joel@....id.au,
	linux-aspeed@...ts.ozlabs.org, conor+dt@...nel.org,
	linux-gpio@...r.kernel.org, devicetree@...r.kernel.org,
	krzk+dt@...nel.org, mani@...nel.org, kishon@...nel.org,
	lpieralisi@...nel.org, openbmc@...ts.ozlabs.org,
	p.zabel@...gutronix.de, linux-pci@...r.kernel.org,
	kwilczynski@...nel.org, vkoul@...nel.org, linus.walleij@...aro.org,
	andrew@...econstruct.com.au, linux-phy@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v3 02/10] dt-bindings: phy: aspeed: Add ASPEED PCIe PHY


On Mon, 01 Sep 2025 13:59:14 +0800, Jacky Chou wrote:
> Introduce device-binding for ASPEED AST2600/2700 PCIe PHY.
> The PCIe PHY is used for PCIe RC to configure as RC mode.
> 
> Signed-off-by: Jacky Chou <jacky_chou@...eedtech.com>
> ---
>  .../bindings/phy/aspeed,ast2600-pcie-phy.yaml | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/aspeed,ast2600-pcie-phy.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@...nel.org>


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