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Message-ID: <7e308b8efe977c4912079b4d1b1ab3d24908559e.1756799774.git.michal.simek@amd.com>
Date: Tue, 2 Sep 2025 09:56:18 +0200
From: Michal Simek <michal.simek@....com>
To: <linux-kernel@...r.kernel.org>, <monstr@...str.eu>,
<michal.simek@...inx.com>, <git@...inx.com>
CC: Quanyang Wang <quanyang.wang@...driver.com>, Conor Dooley
<conor+dt@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Rob Herring
<robh@...nel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE
BINDINGS" <devicetree@...r.kernel.org>, "moderated list:ARM/ZYNQ
ARCHITECTURE" <linux-arm-kernel@...ts.infradead.org>
Subject: [PATCH 1/4] arm64: zynqmp: Disable coresight by default
From: Quanyang Wang <quanyang.wang@...driver.com>
When secure-boot mode of bootloader is enabled, the registers of
coresight are not permitted to access that's why disable it by default.
Signed-off-by: Quanyang Wang <quanyang.wang@...driver.com>
Signed-off-by: Michal Simek <michal.simek@....com>
---
arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 5f26649c9e11..938b014ca923 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -550,6 +550,7 @@ cpu0_debug: debug@...10000 {
reg = <0x0 0xfec10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu0>;
+ status = "disabled";
};
cpu1_debug: debug@...10000 {
@@ -557,6 +558,7 @@ cpu1_debug: debug@...10000 {
reg = <0x0 0xfed10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu1>;
+ status = "disabled";
};
cpu2_debug: debug@...10000 {
@@ -564,6 +566,7 @@ cpu2_debug: debug@...10000 {
reg = <0x0 0xfee10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu2>;
+ status = "disabled";
};
cpu3_debug: debug@...10000 {
@@ -571,6 +574,7 @@ cpu3_debug: debug@...10000 {
reg = <0x0 0xfef10000 0x0 0x1000>;
clock-names = "apb_pclk";
cpu = <&cpu3>;
+ status = "disabled";
};
/* GDMA */
--
2.43.0
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