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Message-Id: <20250903-clk-eyeq7-v1-2-3f5024b5d6e2@bootlin.com>
Date: Wed, 03 Sep 2025 14:47:09 +0200
From: Benoît Monin <benoit.monin@...tlin.com>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
Gregory CLEMENT <gregory.clement@...tlin.com>,
Théo Lebrun <theo.lebrun@...tlin.com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
Sari Khoury <sari.khoury@...ileye.com>,
Benoît Monin <benoit.monin@...tlin.com>
Subject: [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h
Rename the header from mobileye,eyeq5-clk.h to mobileye,eyeq-clk.h as
it covers more SoCs than just the eyeQ5, but also the eyeQ6L and
eyeQ6H.
Also changes all includes to point to the renamed header.
Signed-off-by: Benoît Monin <benoit.monin@...tlin.com>
---
MAINTAINERS | 2 +-
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 +-
arch/mips/boot/dts/mobileye/eyeq6h.dtsi | 2 +-
drivers/clk/clk-eyeq.c | 2 +-
.../dt-bindings/clock/{mobileye,eyeq5-clk.h => mobileye,eyeq-clk.h} | 4 ++--
5 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 6dcfbd11efef87927041f5cf58d70633dbb4b18d..c56f17e4c585fe3e719fbae18b70a0c132c5da48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17112,7 +17112,7 @@ F: arch/mips/mobileye/board-epm5.its.S
F: drivers/clk/clk-eyeq.c
F: drivers/pinctrl/pinctrl-eyeq5.c
F: drivers/reset/reset-eyeq.c
-F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
+F: include/dt-bindings/clock/mobileye,eyeq-clk.h
MODULE SUPPORT
M: Luis Chamberlain <mcgrof@...nel.org>
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 36a73e8a63a1ab32d1c300d17c4491b175428cdf..206afeff80ccf618fae80a832ee2268cad598f71 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
/ {
#address-cells = <2>;
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 5ae939d25ea87ddc15cb848c249beed3d07e32e0..a6ffdf1764b3e66295ee17b2d0d2eee8024f95f3 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -5,7 +5,7 @@
#include <dt-bindings/interrupt-controller/mips-gic.h>
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
/ {
#address-cells = <2>;
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index ea1c3d78e7cd47c2698483f58ae1d691ce6d399d..8fbc8eb31185a9e82216a38a81dfbdaa1a700858 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -44,7 +44,7 @@
#include <linux/spinlock.h>
#include <linux/types.h>
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
#define PCSR0_DAC_EN BIT(0)
diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq-clk.h
similarity index 93%
rename from include/dt-bindings/clock/mobileye,eyeq5-clk.h
rename to include/dt-bindings/clock/mobileye,eyeq-clk.h
index f353c2988035f7c9fb84e4b59c6c4a220436454b..8424ec59a02d037ddd5b049cb4b7f26764ae2542 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h
@@ -3,8 +3,8 @@
* Copyright (C) 2024 Mobileye Vision Technologies Ltd.
*/
-#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
-#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H
#define EQ5C_PLL_CPU 0
#define EQ5C_PLL_VMP 1
--
2.51.0
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