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Message-Id: <20250903-clk-eyeq7-v1-4-3f5024b5d6e2@bootlin.com> Date: Wed, 03 Sep 2025 14:47:11 +0200 From: Benoît Monin <benoit.monin@...tlin.com> To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>, Gregory CLEMENT <gregory.clement@...tlin.com>, Théo Lebrun <theo.lebrun@...tlin.com>, Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Thomas Bogendoerfer <tsbogend@...ha.franken.de>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de> Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>, linux-mips@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org, Tawfik Bayouk <tawfik.bayouk@...ileye.com>, Sari Khoury <sari.khoury@...ileye.com>, Benoît Monin <benoit.monin@...tlin.com> Subject: [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes Add the clock indexes for the various OLB found in the eyeQ7H SoC. For some of the OLB, the indexes are common between two or three blocks: * EQ7HC_DDR defines the clock indexes of DDR0 and DDR1 OLB. * EQ7HC_MIPS defines the clock indexes of MIPS0, MIPS1, and MIPS2 OLB. * EQ7HC_ACC defines the clock indexes of ACC0 and ACC1 OLB. * EQ7HC_XNN defines the clock indexes of XNN0 and XNN1 OLB. Signed-off-by: Benoît Monin <benoit.monin@...tlin.com> --- include/dt-bindings/clock/mobileye,eyeq-clk.h | 110 ++++++++++++++++++++++++++ 1 file changed, 110 insertions(+) diff --git a/include/dt-bindings/clock/mobileye,eyeq-clk.h b/include/dt-bindings/clock/mobileye,eyeq-clk.h index 8424ec59a02d037ddd5b049cb4b7f26764ae2542..0fe9b98c940cbc479ce46fc83fc651101bf1b86a 100644 --- a/include/dt-bindings/clock/mobileye,eyeq-clk.h +++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h @@ -62,4 +62,114 @@ #define EQ6HC_ACC_PLL_MPC 3 #define EQ6HC_ACC_PLL_NOC 4 +#define EQ7HC_SOUTH_PLL_XSPI 0 +#define EQ7HC_SOUTH_PLL_VDIO 1 +#define EQ7HC_SOUTH_PLL_PER 2 +#define EQ7HC_SOUTH_PLL_100P0 3 + +#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS 4 +#define EQ7HC_SOUTH_DIV_PMA_CMN_REF 5 +#define EQ7HC_SOUTH_DIV_REF_UFS 6 +#define EQ7HC_SOUTH_DIV_REF_100P0 7 +#define EQ7HC_SOUTH_DIV_XSPI_SYS 8 +#define EQ7HC_SOUTH_DIV_XSPI_MBITS 9 +#define EQ7HC_SOUTH_DIV_NOC_S 10 +#define EQ7HC_SOUTH_DIV_PCIE_SYS 11 +#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBITS 12 +#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY 13 +#define EQ7HC_SOUTH_DIV_UFS_CORE 14 +#define EQ7HC_SOUTH_DIV_UFS_SMS 15 +#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS 16 +#define EQ7HC_SOUTH_DIV_ETH_SYS 17 +#define EQ7HC_SOUTH_DIV_ETH_MBITS 18 +#define EQ7HC_SOUTH_DIV_CFG_S 19 +#define EQ7HC_SOUTH_DIV_TSU 20 +#define EQ7HC_SOUTH_DIV_VDIO 21 +#define EQ7HC_SOUTH_DIV_VDIO_CORE 22 +#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIT 23 +#define EQ7HC_SOUTH_DIV_VDO_CORE_MBITS 24 +#define EQ7HC_SOUTH_DIV_VDO_P 25 +#define EQ7HC_SOUTH_DIV_VDIO_CFG 26 +#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC 27 + +#define EQ7HC_EAST_PLL_106P6 0 +#define EQ7HC_EAST_PLL_NOC 1 +#define EQ7HC_EAST_PLL_ISP 2 +#define EQ7HC_EAST_PLL_VEU 3 + +#define EQ7HC_EAST_DIV_REF_DDR_PHY 4 +#define EQ7HC_EAST_DIV_REF_106P6 5 +#define EQ7HC_EAST_DIV_CORE 6 +#define EQ7HC_EAST_DIV_CORE_MBITS 7 +#define EQ7HC_EAST_DIV_ISRAM_MBITS 8 +#define EQ7HC_EAST_DIV_CFG 9 +#define EQ7HC_EAST_DIV_VEU_CORE 10 +#define EQ7HC_EAST_DIV_VEU_MBITS 11 +#define EQ7HC_EAST_DIV_VEU_OCP 12 +#define EQ7HC_EAST_DIV_LBITS 13 +#define EQ7HC_EAST_DIV_ISP0_CORE 14 + +#define EQ7HC_WEST_PLL_106P6 0 +#define EQ7HC_WEST_PLL_NOC 1 +#define EQ7HC_WEST_PLL_GPU 2 +#define EQ7HC_WEST_PLL_SSI 3 + +#define EQ7HC_WEST_DIV_GPU 4 +#define EQ7HC_WEST_DIV_GPU_MBITS 5 +#define EQ7HC_WEST_DIV_LBITS 6 +#define EQ7HC_WEST_DIV_MIPS_TIMER 7 +#define EQ7HC_WEST_DIV_SSI_CORE 8 +#define EQ7HC_WEST_DIV_SSI_CORE_MBITS 9 +#define EQ7HC_WEST_DIV_SSI_ROM 10 +#define EQ7HC_WEST_DIV_SSI_ROM_MBITS 11 +#define EQ7HC_WEST_DIV_REF_DDR_PHY 12 +#define EQ7HC_WEST_DIV_REF_106P6 13 +#define EQ7HC_WEST_DIV_CORE 14 +#define EQ7HC_WEST_DIV_CORE_MBIT 15 +#define EQ7HC_WEST_DIV_CFG 16 +#define EQ7HC_WEST_DIV_CAU 17 +#define EQ7HC_WEST_DIV_CAU_MBITS 18 + +#define EQ7HC_PERIPH_EAST_PLL_PER 0 + +#define EQ7HC_PERIPH_EAST_DIV_PER 1 + +#define EQ7HC_PERIPH_WEST_PLL_PER 0 +#define EQ7HC_PERIPH_WEST_PLL_I2S 1 + +#define EQ7HC_PERIPH_WEST_DIV_PER 2 +#define EQ7HC_PERIPH_WEST_DIV_I2S 3 + +#define EQ7HC_DDR_PLL 0 + +#define EQ7HC_DDR_DIV_APB 1 +#define EQ7HC_DDR_DIV_PLLREF 2 +#define EQ7HC_DDR_DIV_DFI 3 + +#define EQ7HC_MIPS_PLL_CPU 0 + +#define EQ7HC_MIPS_DIV_CM 1 + +#define EQ7HC_ACC_PLL_VMP 0 +#define EQ7HC_ACC_PLL_MPC 1 +#define EQ7HC_ACC_PLL_PMA 2 +#define EQ7HC_ACC_PLL_NOC 3 + +#define EQ7HC_ACC_DIV_PMA 4 +#define EQ7HC_ACC_DIV_NCORE 5 +#define EQ7HC_ACC_DIV_CFG 6 + +#define EQ7HC_XNN_PLL_XNN0 0 +#define EQ7HC_XNN_PLL_XNN1 1 +#define EQ7HC_XNN_PLL_XNN2 2 +#define EQ7HC_XNN_PLL_CLSTR 3 + +#define EQ7HC_XNN_DIV_XNN0 4 +#define EQ7HC_XNN_DIV_XNN1 5 +#define EQ7HC_XNN_DIV_XNN2 6 +#define EQ7HC_XNN_DIV_CLSTR 7 +#define EQ7HC_XNN_DIV_I2 8 +#define EQ7HC_XNN_DIV_I2_SMS 9 +#define EQ7HC_XNN_DIV_CFG 10 + #endif -- 2.51.0
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