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Message-Id: <20250903-clk-eyeq7-v1-10-3f5024b5d6e2@bootlin.com>
Date: Wed, 03 Sep 2025 14:47:17 +0200
From: Benoît Monin <benoit.monin@...tlin.com>
To: Vladimir Kondratiev <vladimir.kondratiev@...ileye.com>,
Gregory CLEMENT <gregory.clement@...tlin.com>,
Théo Lebrun <theo.lebrun@...tlin.com>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Thomas Bogendoerfer <tsbogend@...ha.franken.de>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-clk@...r.kernel.org,
Tawfik Bayouk <tawfik.bayouk@...ileye.com>,
Sari Khoury <sari.khoury@...ileye.com>,
Benoît Monin <benoit.monin@...tlin.com>
Subject: [PATCH 10/19] clk: eyeq: skip post-divisor when computing pll
divisor
The output of the pll is routed before the post-divisor so ignore it
when computing the frequency of the pll, functional change is
implemented to reflect how the clock signal is wired internally.
Signed-off-by: Benoît Monin <benoit.monin@...tlin.com>
---
drivers/clk/clk-eyeq.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 8fbc8eb31185a9e82216a38a81dfbdaa1a700858..cbba4a21cca47efb8ab554ecf7322e47437c9c6a 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -177,8 +177,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
*mult = FIELD_GET(PCSR0_INTIN, r0);
*div = FIELD_GET(PCSR0_REF_DIV, r0);
- if (r0 & PCSR0_FOUTPOSTDIV_EN)
- *div *= FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0);
/* Fractional mode, in 2^20 (0x100000) parts. */
if (r0 & PCSR0_DSM_EN) {
--
2.51.0
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