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Message-ID: <811782dd-3240-4af1-a42b-8a6cf49739e5@intel.com>
Date: Tue, 2 Sep 2025 19:34:07 -0700
From: Reinette Chatre <reinette.chatre@...el.com>
To: Babu Moger <babu.moger@....com>, <corbet@....net>, <tony.luck@...el.com>,
<tglx@...utronix.de>, <mingo@...hat.com>, <bp@...en8.de>,
<dave.hansen@...ux.intel.com>
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Subject: Re: [PATCH v17 22/33] x86/resctrl: Implement
resctrl_arch_reset_cntr() and resctrl_arch_cntr_read()
Hi Babu,
On 8/14/25 7:25 PM, Babu Moger wrote:
> System software reads resctrl event data for a particular resource by
> writing the RMID and Event Identifier (EvtID) to the QM_EVTSEL register and
> then reading the event data from the QM_CTR register.
>
> In ABMC mode, the event data of a specific counter ID is read by setting
> the following fields: QM_EVTSEL.ExtendedEvtID = 1, QM_EVTSEL.EvtID =
> L3CacheABMC (=1) and setting QM_EVTSEL.RMID to the desired counter ID.
> Reading the QM_CTR then returns the contents of the specified counter ID.
> RMID_VAL_ERROR bit is set if the counter configuration is invalid, or
> if an invalid counter ID is set in the QM_EVTSEL.RMID field.
> RMID_VAL_UNAVAIL bit is set if the counter data is unavailable.
>
> Introduce resctrl_arch_reset_cntr() and resctrl_arch_cntr_read() to reset
> and read event data for a specific counter.
>
> Signed-off-by: Babu Moger <babu.moger@....com>
> ---
Reviewed-by: Reinette Chatre <reinette.chatre@...el.com>
Reinette
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