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Message-Id: <20250903144217.837448-1-guoren@kernel.org>
Date: Wed, 3 Sep 2025 10:42:17 -0400
From: guoren@...nel.org
To: tjeznach@...osinc.com,
joro@...tes.org,
will@...nel.org,
robin.murphy@....com
Cc: guoren@...nel.org,
paul.walmsley@...ive.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
palmer@...belt.com,
iommu@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] iommu/riscv: Use two individual 4-byte accesses for 8-byte register
From: "Guo Ren (Alibaba DAMO Academy)" <guoren@...nel.org>
The RISC-V IOMMU memory-mapped register interface define:
The 8-byte IOMMU registers are defined in such a way that
software can perform two individual 4-byte accesses.
Therefore, use two individual 4-byte accesses for an 8-byte
register to make the driver compatible with a 32-bit-wide
interconnect.
Signed-off-by: Guo Ren (Alibaba DAMO Academy) <guoren@...nel.org>
---
drivers/iommu/riscv/iommu.c | 7 +++++--
drivers/iommu/riscv/iommu.h | 27 ++++++++++++++++++++-------
2 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
index 0eae2f4bdc5e..9a80464ed7be 100644
--- a/drivers/iommu/riscv/iommu.c
+++ b/drivers/iommu/riscv/iommu.c
@@ -662,9 +662,12 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu)
#define riscv_iommu_read_ddtp(iommu) ({ \
u64 ddtp; \
- riscv_iommu_readq_timeout((iommu), RISCV_IOMMU_REG_DDTP, ddtp, \
- !(ddtp & RISCV_IOMMU_DDTP_BUSY), 10, \
+ u32 ddtp_lo, ddtp_hi; \
+ riscv_iommu_readl_timeout((iommu), RISCV_IOMMU_REG_DDTP, ddtp_lo, \
+ !(ddtp_lo & RISCV_IOMMU_DDTP_BUSY), 10, \
RISCV_IOMMU_DDTP_TIMEOUT); \
+ ddtp_hi = riscv_iommu_readl(iommu, RISCV_IOMMU_REG_DDTP + 4); \
+ ddtp = ((u64)ddtp_hi << 32) | ddtp_lo; \
ddtp; })
static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu)
diff --git a/drivers/iommu/riscv/iommu.h b/drivers/iommu/riscv/iommu.h
index 46df79dd5495..698acffff298 100644
--- a/drivers/iommu/riscv/iommu.h
+++ b/drivers/iommu/riscv/iommu.h
@@ -69,18 +69,31 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu);
#define riscv_iommu_readl(iommu, addr) \
readl_relaxed((iommu)->reg + (addr))
-#define riscv_iommu_readq(iommu, addr) \
- readq_relaxed((iommu)->reg + (addr))
+static inline u64 riscv_iommu_readq(struct riscv_iommu_device *iommu,
+ u16 addr)
+{
+ u32 val_lo, val_hi;
+
+ val_lo = readl_relaxed((iommu)->reg + (addr));
+ val_hi = readl_relaxed((iommu)->reg + (addr) + 4);
+
+ return (u64) val_lo | ((u64) val_hi << 32);
+}
#define riscv_iommu_writel(iommu, addr, val) \
writel_relaxed((val), (iommu)->reg + (addr))
-#define riscv_iommu_writeq(iommu, addr, val) \
- writeq_relaxed((val), (iommu)->reg + (addr))
+static inline void riscv_iommu_writeq(struct riscv_iommu_device *iommu,
+ u16 addr, u64 val)
+{
+ u32 val_lo, val_hi;
-#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
- readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
- delay_us, timeout_us)
+ val_hi = (u32) (val >> 32);
+ val_lo = (u32) val;
+
+ writel_relaxed((val_hi), (iommu)->reg + (addr) + 4);
+ writel_relaxed((val_lo), (iommu)->reg + (addr));
+}
#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \
--
2.40.1
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