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Message-Id: <20250616-rk3588-csi-dphy-v4-7-a4f340a7f0cf@collabora.com>
Date: Wed, 03 Sep 2025 19:04:55 +0200
From: Michael Riesch via B4 Relay <devnull+michael.riesch.collabora.com@...nel.org>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Heiko Stuebner <heiko@...ech.de>,
Vinod Koul <vkoul@...nel.org>, Kishon Vijay Abraham I <kishon@...nel.org>,
Philipp Zabel <p.zabel@...gutronix.de>,
Kever Yang <kever.yang@...k-chips.com>,
Jagan Teki <jagan@...rulasolutions.com>,
Sebastian Reichel <sebastian.reichel@...labora.com>,
Diederik de Haas <didi.debian@...ow.org>,
Neil Armstrong <neil.armstrong@...aro.org>,
Heiko Stuebner <heiko@...ech.de>,
Collabora Kernel Team <kernel@...labora.com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-rockchip@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-phy@...ts.infradead.org,
Michael Riesch <michael.riesch@...labora.com>
Subject: [PATCH v4 7/7] arm64: dts: rockchip: add mipi csi-2 dphy nodes to
rk3588
From: Michael Riesch <michael.riesch@...labora.com>
The Rockchip RK3588 features two MIPI CSI-2 DPHYs. Add the device
tree nodes for them.
Signed-off-by: Michael Riesch <michael.riesch@...labora.com>
---
arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 34 +++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 70f03e68ba55..72a0022d1b74 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -621,6 +621,16 @@ php_grf: syscon@...b0000 {
reg = <0x0 0xfd5b0000 0x0 0x1000>;
};
+ csidphy0_grf: syscon@...b4000 {
+ compatible = "rockchip,rk3588-csidphy-grf", "syscon";
+ reg = <0x0 0xfd5b4000 0x0 0x1000>;
+ };
+
+ csidphy1_grf: syscon@...b5000 {
+ compatible = "rockchip,rk3588-csidphy-grf", "syscon";
+ reg = <0x0 0xfd5b5000 0x0 0x1000>;
+ };
+
pipe_phy0_grf: syscon@...bc000 {
compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
reg = <0x0 0xfd5bc000 0x0 0x100>;
@@ -3055,6 +3065,30 @@ mipidcphy1: phy@...b0000 {
status = "disabled";
};
+ csi_dphy0: phy@...c0000 {
+ compatible = "rockchip,rk3588-csi-dphy";
+ reg = <0x0 0xfedc0000 0x0 0x8000>;
+ clocks = <&cru PCLK_CSIPHY0>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ resets = <&cru SRST_P_CSIPHY0>, <&cru SRST_CSIPHY0>;
+ reset-names = "apb", "phy";
+ rockchip,grf = <&csidphy0_grf>;
+ status = "disabled";
+ };
+
+ csi_dphy1: phy@...c8000 {
+ compatible = "rockchip,rk3588-csi-dphy";
+ reg = <0x0 0xfedc8000 0x0 0x8000>;
+ clocks = <&cru PCLK_CSIPHY1>;
+ clock-names = "pclk";
+ #phy-cells = <0>;
+ resets = <&cru SRST_P_CSIPHY1>, <&cru SRST_CSIPHY1>;
+ reset-names = "apb", "phy";
+ rockchip,grf = <&csidphy1_grf>;
+ status = "disabled";
+ };
+
combphy0_ps: phy@...00000 {
compatible = "rockchip,rk3588-naneng-combphy";
reg = <0x0 0xfee00000 0x0 0x100>;
--
2.39.5
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