linux-kernel - [PATCH v2 3/8] dt-bindings: memory: tegra210: emc: Document OPP table and interconnect

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Message-Id: <20250903-t210-actmon-v2-3-e0d534d4f8ea@gmail.com>
Date: Wed, 03 Sep 2025 14:50:09 -0500
From: Aaron Kling via B4 Relay <devnull+webgeek1234.gmail.com@...nel.org>
To: Krzysztof Kozlowski <krzk@...nel.org>, Rob Herring <robh@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, 
 Thierry Reding <thierry.reding@...il.com>, 
 Jonathan Hunter <jonathanh@...dia.com>, 
 Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 MyungJoo Ham <myungjoo.ham@...sung.com>, 
 Kyungmin Park <kyungmin.park@...sung.com>, 
 Chanwoo Choi <cw00.choi@...sung.com>, Dmitry Osipenko <digetx@...il.com>
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, 
 linux-tegra@...r.kernel.org, linux-pm@...r.kernel.org, 
 Aaron Kling <webgeek1234@...il.com>
Subject: [PATCH v2 3/8] dt-bindings: memory: tegra210: emc: Document OPP
 table and interconnect

From: Aaron Kling <webgeek1234@...il.com>

These are needed for dynamic frequency scaling of the EMC controller.

Signed-off-by: Aaron Kling <webgeek1234@...il.com>
---
 .../bindings/memory-controllers/nvidia,tegra210-emc.yaml    | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
index bc8477e7ab193b7880bb681037985f3fccebf02f..6cc1c7fc7a328bd18c7c0beb535c1ff918bcdb2a 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml
@@ -33,6 +33,9 @@ properties:
     items:
       - description: EMC general interrupt
 
+  "#interconnect-cells":
+    const: 0
+
   memory-region:
     maxItems: 1
     description:
@@ -44,12 +47,19 @@ properties:
     description:
       phandle of the memory controller node
 
+  operating-points-v2:
+    description:
+      Should contain freqs and voltages and opp-supported-hw property, which
+      is a bitfield indicating SoC speedo ID mask.
+
 required:
   - compatible
   - reg
   - clocks
   - clock-names
+  - "#interconnect-cells"
   - nvidia,memory-controller
+  - operating-points-v2
 
 additionalProperties: false
 
@@ -79,4 +89,7 @@ examples:
         interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
         memory-region = <&emc_table>;
         nvidia,memory-controller = <&mc>;
+        operating-points-v2 = <&dvfs_opp_table>;
+
+        #interconnect-cells = <0>;
     };

-- 
2.50.1