linux-kernel - Re: [PATCH v8 2/2] ARM: dts: aspeed: Add NVIDIA GB200 UT3.0b board

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Message-ID: <c9348ebb7f0cd24c950ba07abf4641a1d5382160.camel@codeconstruct.com.au>
Date: Wed, 03 Sep 2025 15:16:36 +0930
From: Andrew Jeffery <andrew@...econstruct.com.au>
To: Donald Shannon <donalds@...dia.com>, robh@...nel.org,
 krzk+dt@...nel.org,  conor+dt@...nel.org
Cc: joel@....id.au, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-aspeed@...ts.ozlabs.org, 
	linux-kernel@...r.kernel.org, openbmc@...ts.ozlabs.org
Subject: Re: [PATCH v8 2/2] ARM: dts: aspeed: Add NVIDIA GB200 UT3.0b board

Hi Donald,

Sorry for the delay.

On Fri, 2025-08-15 at 15:43 -0700, Donald Shannon wrote:
> This is an Aspeed AST2600 based unit testing platform for GB200.
> UT3.0b is different than nvidia-gb200nvl-bmc due to networking topology
> differences, additional gpio expanders, and voltage regulator gating
> some devices.
> 
> Reference to Ast2600 SOC [1].
> Reference to Blackwell GB200NVL Platform [2].
> 
> Link: https://www.aspeedtech.com/server_ast2600/ [1]
> Link: https://nvdam.widen.net/s/wwnsxrhm2w/blackwell-datasheet-3384703 [2]
> Signed-off-by: Donald Shannon <donalds@...dia.com>
> ---
>  arch/arm/boot/dts/aspeed/Makefile             |    1 +
>  .../aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts  | 1030 +++++++++++++++++
>  2 files changed, 1031 insertions(+)
>  create mode 100644 arch/arm/boot/dts/aspeed/aspeed-bmc-nvidia-gb200-ut30b.dts
> 
> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> index aba7451ab749..37edc4625a9f 100644
> --- a/arch/arm/boot/dts/aspeed/Makefile
> +++ b/arch/arm/boot/dts/aspeed/Makefile
> 

*snip*

> +&gpio0 {
> +       gpio-line-names =
> +               /*A0-A7*/ "", "", "", "", "", "", "", "",
> +               /*B0-B7*/ "", "", "", "", "", "", "", "",
> +               /*C0-C7*/ "SGPIO_I2C_MUX_SEL-O", "", "", "", "", "", "", "",
> +               /*D0-D7*/ "", "", "", "UART1_MUX_SEL-O", "", "FPGA_PEX_RST_L-O", "", "",
> +               /*E0-E7*/ "RTL8221_PHY_RST_L-O", "RTL8211_PHY_INT_L-I", "", "UART3_MUX_SEL-O",
> +                                       "", "", "", "SGPIO_BMC_EN-O",
> +               /*F0-F7*/ "", "", "", "", "", "", "", "",
> +               /*G0-G7*/ "", "", "", "", "", "", "", "",
> +               /*H0-H7*/ "", "", "", "", "", "", "", "",
> +               /*I0-I7*/ "", "", "", "", "", "QSPI2_RST_L-O", "GLOBAL_WP_BMC-O", "BMC_DDR4_TEN-O",
> +               /*J0-J7*/ "", "", "", "", "", "", "", "",
> +               /*K0-K7*/ "", "", "", "", "", "", "", "",
> +               /*L0-L7*/ "", "", "", "", "", "", "", "",
> +               /*M0-M7*/ "PCIE_EP_RST_EN-O", "BMC_FRU_WP-O", "FPGA_RST_L-O", "STBY_POWER_EN-O",
> +                                       "STBY_POWER_PG-I", "PCIE_EP_RST_L-O", "", "",
> +               /*N0-N7*/ "", "", "", "", "", "", "", "",
> +               /*O0-O7*/ "", "", "", "", "", "", "", "",
> +               /*P0-P7*/ "", "", "", "", "", "", "", "",
> +               /*Q0-Q7*/ "", "", "", "", "", "", "", "",
> +               /*R0-R7*/ "", "", "", "", "", "", "", "",
> +               /*S0-S7*/ "", "", "", "", "", "", "", "",
> +               /*T0-T7*/ "", "", "", "", "", "", "", "",
> +               /*U0-U7*/ "", "", "", "", "", "", "", "",
> +               /*V0-V7*/ "AP_EROT_REQ-O", "EROT_AP_GNT-I", "", "","PCB_TEMP_ALERT-I", "","", "",
> +               /*W0-W7*/ "", "", "", "", "", "", "", "",
> +               /*X0-X7*/ "", "", "TPM_MUX_SEL-O", "", "", "", "", "",
> +               /*Y0-Y7*/ "", "", "", "EMMC_RST-O", "","", "", "",
> +               /*Z0-Z7*/ "BMC_READY-O","", "", "", "", "", "", "";
> +};
> +
> +&gpio1 {
> +       /* 36 1.8V GPIOs */
> +       gpio-line-names =
> +               /*A0-A7*/ "", "", "", "", "", "", "", "",
> +               /*B0-B7*/ "", "", "", "", "", "", "IO_EXPANDER_INT_L-I","",
> +               /*C0-C7*/ "", "", "", "", "", "", "", "",
> +               /*D0-D7*/ "", "", "", "", "", "", "SPI_HOST_TPM_RST_L-O", "SPI_BMC_FPGA_INT_L-I",
> +               /*E0-E7*/ "", "", "", "", "", "", "", "";
> +};
> +
> +&sgpiom0 {

So the style guide asks the referenced nodes to be ordered either
alphabetically, or in DTSI order[1] (which should be unit-address
order).

[1]: https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes

What we have to the quoted section above isn't in alphabetical order.
To this point it was DTSI order, but that breaks here too.

My preference is that nodes in the DTS referencing the DTSI are
alphabetical (as we can't see the unit address for ordering). Can you
please fix it?

You mention in your cover letter that ordering was addressed in v3 -
did we lose that along the way?

*snip*

> +
> +&uart_routing { };

Drop this?

Cheers,

Andrew