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Message-Id: <20250903080404.3260135-5-quic_sartgarg@quicinc.com>
Date: Wed, 3 Sep 2025 13:34:04 +0530
From: Sarthak Garg <quic_sartgarg@...cinc.com>
To: Ulf Hansson <ulf.hansson@...aro.org>, Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>,
Adrian Hunter <adrian.hunter@...el.com>
Cc: linux-mmc@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-msm@...r.kernel.org,
quic_nguyenb@...cinc.com, quic_rampraka@...cinc.com,
quic_pragalla@...cinc.com, quic_sayalil@...cinc.com,
quic_nitirawa@...cinc.com, quic_bhaskarv@...cinc.com,
kernel@....qualcomm.com, Sarthak Garg <quic_sartgarg@...cinc.com>
Subject: [PATCH V5 4/4] arm64: dts: qcom: sm8550: Add max-sd-hs-hz property
Due to board-specific hardware constraints particularly related
to level shifter in this case the maximum frequency for SD High-Speed
(HS) mode must be limited to 37.5 MHz to ensure reliable operation of SD
card in HS mode.
This is achieved by introducing the `max-sd-hs-hz` property in the
device tree, allowing the controller to operate within safe frequency
limits for HS mode.
Signed-off-by: Sarthak Garg <quic_sartgarg@...cinc.com>
---
arch/arm64/boot/dts/qcom/sm8550.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 82cabf777cd2..3692a3a49634 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3189,6 +3189,7 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
&config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
bus-width = <4>;
+ max-sd-hs-hz = <37500000>;
dma-coherent;
/* Forbid SDR104/SDR50 - broken hw! */
--
2.34.1
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